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Jafar Savoj
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2010 – 2019
- 2015
- [j8]Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang:
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. IEEE J. Solid State Circuits 50(8): 1932-1944 (2015) - [c15]Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang:
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. ISSCC 2015: 1-3 - 2014
- [c14]Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang:
Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. CICC 2014: 1-4 - [c13]Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, Ken Chang:
2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS. ISSCC 2014: 52-53 - 2013
- [j7]Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang:
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. IEEE J. Solid State Circuits 48(11): 2582-2594 (2013) - [c12]Jafar Savoj, Chris Mangelsdorf:
Session 10 overview: Analog techniques. ISSCC 2013: 170-171 - [c11]Boris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu:
F6: Mixed-signal/RF design and modeling in next-generation CMOS. ISSCC 2013: 510-511 - 2012
- [c10]Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Zhaoyin Daniel Wu, Elad Alon, Ken Chang:
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS. CICC 2012: 1-4 - [c9]Jafar Savoj, Chris Mangelsdorf:
Session 21 overview: Analog techniques: Analog subcommittee. ISSCC 2012: 356-357 - [c8]Jed Hurwitz, Jafar Savoj:
Technologies that could change the world - You decide! ISSCC 2012: 515 - [c7]Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang:
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS. VLSIC 2012: 104-105 - 2011
- [j6]Jafar Savoj, Yiannos Manoli, Hooman Darabi, Yorgos Palaskas, Michael Moyal:
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 46(12): 2739-2744 (2011) - [c6]Ali Sheikholeslami, Franz Dielacher
, Miki Moyal, Jafar Savoj, John T. Stonick, Takuji Yamamoto:
High-speed transceivers: Standards, challenges, and future. ISSCC 2011: 522-523
2000 – 2009
- 2008
- [j5]Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. IEEE J. Solid State Circuits 43(4): 999-1009 (2008) - [j4]Jafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp:
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications. IEEE J. Solid State Circuits 43(5): 1207-1216 (2008) - 2007
- [c5]Amir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz:
Time-Variant Characterization and Compensation of Wideband Circuits. CICC 2007: 487-490 - [c4]Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz:
A new technique for characterization of digital-to-analog converters in high-speed systems. DATE 2007: 433-438 - 2005
- [j3]Albert Z. H. Wang, Sreedhar Natarajan, Jafar Savoj:
Introduction to the Special Issue on the IEEE 2004 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 40(9): 1775-1777 (2005) - [c3]Jafar Savoj, Ramesh Harjani:
Clocking circuits for wireline communications. CICC 2005: 526-527 - [c2]Jafar Savoj, David Rich, Brett Forejt, Peter R. Kinget
Will continued process-node shrinks kill high-performance analog design? CICC 2005: 616-617 - 2003
- [j2]Jafar Savoj, Behzad Razavi:
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector. IEEE J. Solid State Circuits 38(1): 13-21 (2003) - 2001
- [j1]Jafar Savoj, Behzad Razavi:
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. IEEE J. Solid State Circuits 36(5): 761-768 (2001) - [c1]Jafar Savoj, Behzad Razavi:
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems. DAC 2001: 121-126
Coauthor Index
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