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Zhijing Li 0002
Person information
- affiliation: Cornell University, Thaca, NY, USA
- affiliation (former): Shanghai Jiao Tong University, Shanghai, China
Other persons with the same name
- Zhijing Li 0001 — Facebook, USA (and 2 more)
- Zhijing Li 0003 — Accenture Japan Ltd., Tokyo, Japan
- Zhijing Li 0004
— Hunan University of Science and Technology, School of Information and Electrical Engineering, Xiangtan, China (and 1 more)
- Zhijing Li 0005 — Xi'an Jiaotong University, Xi'an, China
- Zhijing Li 0006 — Lanzhou University of Technology, China
- Zhijing Li 0007
- Zhijing Li 0008 — Guangdong University of Science and Technology, Dongguan, China
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2020 – today
- 2022
- [c4]Zhijing Li, Yuwei Ye, Stephen Neuendorffer, Adrian Sampson
Compiler-Driven Simulation of Reconfigurable Hardware Accelerators. HPCA 2022: 619-632 - [i4]Zhijing Li, Yuwei Ye, Stephen Neuendorffer, Adrian Sampson:
Compiler-Driven Simulation of Reconfigurable Hardware Accelerators. CoRR abs/2202.00739 (2022) - 2021
- [c3]Rachit Nigam
A compiler infrastructure for accelerator generators. ASPLOS 2021: 804-817 - [i3]Rachit Nigam, Samuel Thomas, Zhijing Li, Adrian Sampson:
A Compiler Infrastructure for Accelerator Generators. CoRR abs/2102.09713 (2021) - 2020
- [c2]Ecenur Ustun, Chenhui Deng, Debjit Pal
Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. ICCAD 2020: 87:1-87:9 - [c1]Rachit Nigam
Predictable accelerator design with time-sensitive affine types. PLDI 2020: 393-407 - [i2]Zhijing Li, Christopher De Sa, Adrian Sampson:
Optimizing JPEG Quantization for Classification Networks. CoRR abs/2003.02874 (2020) - [i1]Rachit Nigam, Sachille Atapattu, Samuel Thomas, Zhijing Li, Theodore Bauer, Yuwei Ye, Apurva Koti, Adrian Sampson, Zhiru Zhang:
Predictable Accelerator Design with Time-Sensitive Affine Types. CoRR abs/2004.04852 (2020)
2010 – 2019
- 2019
- [j2]Junjun Hu, Zhijing Li, Meng Yang, Zixin Huang, Weikang Qian:
A high-accuracy approximate adder with correct sign calculation. Integr. 65: 370-388 (2019) - [j1]Zhijing Li
Simultaneous Area and Latency Optimization for Stochastic Circuits by D Flip-Flop Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1251-1264 (2019)
Coauthor Index
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last updated on 2024-10-04 21:04 CEST by the dblp team
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