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Shirshendu Das
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2020 – today
- 2024
- [j17]Atul Kumar, Shirshendu Das
, Basant Subba:
HTree: Hardware Trojan Attack on Cache Resizing Policies. IEEE Embed. Syst. Lett. 16(3): 263-266 (2024) - [j16]Jaspinder Kaur
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks. ACM Trans. Design Autom. Electr. Syst. 29(2): 27:1-27:22 (2024) - [c28]Aditya S. Gangwar, Prathamesh Nitin Tanksale, Shirshendu Das, Sudeepta Mishra:
$\mathcal{F}lush+early\mathcal{R}\text{ELOAD}$: Covert Channels Attack on Shared LLC Using MSHR Merging. DATE 2024: 1-6 - 2023
- [j15]Atul Kumar, Dipika Deb
edAttack: Hardware Trojan Attack on On-Chip Packet Compression. IEEE Des. Test 40(6): 125-135 (2023) - [j14]Jaspinder Kaur
TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks. J. Syst. Archit. 135: 102805 (2023) - [j13]Divyansh Maura
Variation aware power management for GPU memories. Microprocess. Microsystems 96: 104711 (2023) - [c27]Jaspinder Kaur
ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning. ISQED 2023: 1-8 - 2022
- [j12]Sudershan Kumar, Prabuddha Sinha, Shirshendu Das
WinDRAM: Weak rows as in-DRAM cache. Concurr. Comput. Pract. Exp. 34(28) (2022) - [j11]Bharat Bisht, Shirshendu Das
BHT-NoC: Blaming Hardware Trojans in NoC Routers. IEEE Des. Test 39(6): 39-47 (2022) - [j10]Bindu Agarwalla, Shirshendu Das
Process variation aware DRAM-Cache resizing. J. Syst. Archit. 123: 102364 (2022) - [c26]Bindu Agarwalla, Nilkanta Sahu, Shirshendu Das:
PV-aware Replacement Policy for Two-level Shared Cache. iSES 2022: 459-464 - [c25]Kaustav Goswami, Shirshendu Das, Sagar Satapathy, Dip Sankar Banerjee:
A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices. MEMSYS 2022: 3:1-3:16 - [c24]Samiksha Verma, Shirshendu Das, Vipul Bondre:
Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly. MEMSYS 2022: 7:1-7:11 - [i2]Kaustav Goswami, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee:
VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design. CoRR abs/2201.06853 (2022) - [i1]Jaspinder Kaur
TPPD: Targeted Pseudo Partitioning based Defence for Cross-Core Covert Channel Attacks. CoRR abs/2203.12207 (2022) - 2021
- [j9]Jaspinder Kaur, Shirshendu Das
A Survey on Cache Timing Channel Attacks for Multicore Processors. J. Hardw. Syst. Secur. 5(2): 169-189 (2021) - [j8]Bindu Agarwalla
Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors. J. Syst. Archit. 113: 101886 (2021) - [j7]Kaustav Goswami
Towards Enhanced System Efficiency while Mitigating Row Hammer. ACM Trans. Archit. Code Optim. 18(4): 40:1-40:26 (2021) - [c23]Kousik Kumar Dutta, Prathamesh Nitin Tanksale, Shirshendu Das:
A Fairness Conscious Cache Replacement Policy for Last Level Cache. DATE 2021: 695-700 - [c22]Anurag Agarwal, Jaspinder Kaur
Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache. DATE 2021: 1691-1696 - [c21]Tanmay Goel, Divyansh Maura, Kaustav Goswami
Towards Row Sensitive DRAM Refresh through Retention Awareness. ISQED 2021: 450-456 - [c20]Manaal Mukhtar Jamadar, Jaspinder Kaur
MAPCP: Memory Access Pattern Classifying Prefetcher. MEMSYS 2021: 8:1-8:12 - [c19]Shobhit Kumar, Shirshendu Das, Manaal Mukhtar Jamadar, Jaspinder Kaur
Efficient On-chip Communication for Neuromorphic Systems. SmartWorld/SCALCOM/UIC/ATC/IOP/SCI 2021: 234-239
2010 – 2019
- 2019
- [j6]Dipika Deb, John Jose
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines. J. Parallel Distributed Comput. 123: 118-129 (2019) - [c18]Kaustav Goswami
State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency. ISQED 2019: 131-137 - 2018
- [c17]Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor:
Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. VLSID 2018: 31-36 - 2017
- [j5]Shirshendu Das, Hemangee K. Kapoor:
Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets. IEEE Trans. Parallel Distributed Syst. 28(8): 2229-2243 (2017) - [c16]Shirshendu Das, Hemangee K. Kapoor:
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. ISVLSI 2017: 182-187 - 2016
- [j4]Shirshendu Das, Hemangee K. Kapoor:
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture. ACM Trans. Design Autom. Electr. Syst. 22(1): 4:1-4:26 (2016) - [c15]Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs. SAC 2016: 1739-1744 - [c14]Shirshendu Das, Hemangee K. Kapoor:
Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs. SAC 2016: 1745-1750 - [c13]Surajit Das, Shirshendu Das, Hemangee K. Kapoor:
Tag only storage for capacity optimised last level cache in chip multiprocessors. VDAT 2016: 1-6 - [c12]Shirshendu Das, Hemangee K. Kapoor:
Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. VLSID 2016: 92-97 - 2015
- [c11]Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. IPDPS Workshops 2015: 444-453 - [c10]Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty:
Static energy reduction by performance linked cache capacity management in tiled CMPs. SAC 2015: 1913-1918 - [c9]Shirshendu Das, Hemangee K. Kapoor:
Dynamic associativity management using utility based way-sharing. SAC 2015: 1919-1924 - [c8]Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Power aware cache miss reduction by energy efficient victim retention. VDAT 2015: 1-6 - [c7]Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das:
An efficient searching mechanism for dynamic NUCA in chip multiprocessors. VDAT 2015: 1-5 - [c6]Shirshendu Das, Hemangee K. Kapoor:
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs. VLSID 2015: 141-146 - 2014
- [j3]Shirshendu Das, Hemangee K. Kapoor:
Victim retention for reducing cache misses in tiled chip multiprocessors. Microprocess. Microsystems 38(4): 263-275 (2014) - [c5]B. Venkateswarlu Naik, Shirshendu Das, Hemangee K. Kapoor:
RT-DVS for Power Optimization in Multiprocessor Real-Time Systems. ICIT 2014: 24-29 - [c4]M. Lakshmi Prasad, Shirshendu Das, Hemangee K. Kapoor:
An Approach for Multicast Routing in Networks-on-Chip. ICIT 2014: 299-304 - 2013
- [j2]Shirshendu Das, Parasara Sridhar Duggirala, Hemangee K. Kapoor:
A formal framework for interfacing mixed-timing systems. Integr. 46(3): 255-264 (2013) - [j1]Hemangee K. Kapoor, Praveen Kanakala, Malti Verma, Shirshendu Das:
Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors. J. Supercomput. 65(2): 771-796 (2013) - [c3]Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor:
Towards a Better Cache Utilization Using Controlled Cache Partitioning. DASC 2013: 179-186 - [c2]Shirshendu Das, Hemangee K. Kapoor:
Dynamic Associativity Management Using Fellow Sets. ISED 2013: 133-137 - [c1]Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee K. Kapoor:
Random-LRU: A Replacement Policy for Chip Multiprocessors. VDAT 2013: 204-213
Coauthor Index
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last updated on 2024-10-01 21:37 CEST by the dblp team
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