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Teruki Someya
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2020 – today
- 2023
- [c12]Nandor G. Toth
, Zhong Tang, Teruki Someya, Sining Pan, Kofi A. A. Makinwa:
A BJT-Based Temperature Sensor with $\pm 0.1^{\circ}\mathrm{C}(3\sigma)$ Inaccuracy from -55°C to 125°C and a 0.85pJ.K2 Resolution FoM Using Continuous-Time Readout. ISSCC 2023: 358-359 - 2022
- [j8]Yuncheng Zhang, Bangan Liu, Teruki Someya, Rui Wu, Junjun Qiu, Atsushi Shirane, Kenichi Okada:
A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components. IEICE Trans. Electron. 105-C(7): 334-342 (2022) - [j7]Yun Wang
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. IEEE J. Solid State Circuits 57(2): 356-370 (2022) - [c11]Teruki Someya, Vincent Van Hoek, Jan A. Angevare, Sining Pan, Kofi A. A. Makinwa:
A 210nW BJT-based Temperature Sensor with an Inaccuracy of ±0.15°C (3σ) from -15°C to 85°C. VLSI Technology and Circuits 2022: 120-121 - 2021
- [j6]Bangan Liu
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 603-616 (2021) - 2020
- [j5]Zheng Sun, Dingxin Xu, Hongye Huang
A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications. IEICE Trans. Electron. 103-C(10): 505-513 (2020)
2010 – 2019
- 2019
- [j4]Teruki Someya
An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage. IEEE J. Solid State Circuits 54(3): 613-622 (2019) - [j3]Hanli Liu
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. IEEE J. Solid State Circuits 54(12): 3478-3492 (2019) - [j2]Teruki Someya
A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1270-1279 (2019) - [c10]Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC 2019: 267-270 - [c9]Bangan Liu, Yuncheng Zhang
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. CICC 2019: 1-4 - [c8]Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang
A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO. ESSCIRC 2019: 101-104 - [c7]Hanli Liu, Zheng Sun, Hongye Huang
A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. ISSCC 2019: 256-258 - 2018
- [c6]Teruki Someya, Islam A. K. M. Mahfuzul
A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage. CICC 2018: 1-4 - 2017
- [j1]Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier. IEICE Trans. Electron. 100-C(4): 349-358 (2017) - 2016
- [c5]Teruki Someya, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
56-Level programmable voltage detector in steps of 50mV for battery management. A-SSCC 2016: 49-52 - 2015
- [c4]Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting. ESSCIRC 2015: 249-252 - [c3]Hiroshi Fuketa, Masamune Hamamatsu, Tomoyuki Yokota, Wakako Yukita, Teruki Someya, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits. ISSCC 2015: 1-3 - 2013
- [c2]Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada:
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC 2013: 1-4
2000 – 2009
- 2006
- [c1]Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi
An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin. ISSCC 2006: 1060-1069
Coauthor Index
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