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John Safran
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2010 – 2019
- 2015
- [c4]Mukta G. Farooq, Giuseppe La Rosa, Fen Chen, Prakash Periasamy, Troy L. Graves-abe, Chandrasekharan Kothandaraman, C. Collins, W. Landers, J. Oakley, J. Liu, John Safran, S. Ghosh, S. Mittl, D. Ioannou, Carole Graas, Daniel Berger, Subramanian S. Iyer:
Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability. IRPS 2015: 4 - 2013
- [j1]Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM. IEEE J. Solid State Circuits 48(4): 940-947 (2013)
2000 – 2009
- 2008
- [c3]Gregory Uhlmann, Tony Aipperspach, Toshiaki Kirihata, K. Chandrasekharan, Yan Zun Li, Chris Paone, Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian S. Iyer:
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS. ISSCC 2008: 406-407 - 2007
- [c2]Norman Robson, John Safran, Chandrasekharan Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, Alan Leslie, Dan Moy, Toshiaki Kirihata, Subramanian S. Iyer:
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips. CICC 2007: 799-804 - 2003
- [c1]Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner:
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate. ISLPED 2003: 434-439
Coauthor Index
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