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Bhanu Kapoor
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2010 – 2019
- 2015
- [i1]Sapna Saxena, Bhanu Kapoor:
State of the art parallel approaches for RSA public key based cryptosystem. CoRR abs/1503.03593 (2015) - 2011
- [j3]Bhanu Kapoor, Shireesh Verma:
Power Management Design and Verification. J. Low Power Electron. 7(1): 41-48 (2011) - [c10]Bhanu Kapoor, Knut M. Just:
Embedded tutorial: Addressing critical power management verification issues in low power designs. DATE 2011: 124 - [c9]Bhanu Kapoor, Alan Hunter, Prapanna Tiwari:
Power management verification experiences in Wireless SoCs. DATE 2011: 507-508
2000 – 2009
- 2009
- [c8]Albert Chiang, Wei-Hua Han, Bhanu Kapoor:
Validating physical access layer of WiMAX using SystemVerilog. ISQED 2009: 356-359 - [c7]Bhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d'Abreu:
Impact of SoC power management techniques on verification and testing. ISQED 2009: 692-695 - [c6]Bhanu Kapoor:
Special Session 11C: Embedded Tutorial: System-on-a-Chip Power Management Implications on Validation and Testing. VTS 2009: 333 - 2008
- [c5]Bhanu Kapoor, John Goodenough, Shankar Hemmady, Shireesh Verma, Manuel A. d'Abreu, Kaushik Roy:
Panel: SoC power management implications on validation and testing. HLDVT 2008: 135-137 - [c4]Bhanu Kapoor, J. Marc Edwards, Shankar Hemmady, Shireesh Verma, Kaushik Roy:
Tutorial: SoC Power Management Verification and Testing Issues. MTV 2008: 67-72
1990 – 1999
- 1998
- [j2]Lode Nachtergaele, Francky Catthoor, Bhanu Kapoor, Stefan Janssens, Dennis Moolenaar:
Low-power data transfer and storage exploration for H.263 video decoder system. IEEE J. Sel. Areas Commun. 16(1): 120-129 (1998) - [c3]Bhanu Kapoor:
Low Power Memory Architectures for Video Applications. Great Lakes Symposium on VLSI 1998: 2-6 - 1996
- [j1]Bhanu Kapoor, V. S. S. Nair:
Improving Path Sensitizability of Combinational Circuits. VLSI Design 5(1): 49-57 (1996) - 1994
- [c2]Bhanu Kapoor:
Improving the Accuracy of Circuit Activity Measurement. DAC 1994: 734-739 - [c1]Bhanu Kapoor, V. S. S. Nair:
Area, performance, and sensitizable paths [logic design]. Great Lakes Symposium on VLSI 1994: 222-227
Coauthor Index
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