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Xinyi Zhang 0001
Person information
- affiliation: University of Pittsburgh, Pittsburgh, PA, USA
Other persons with the same name
- Xinyi Zhang (aka: Xin-Yi Zhang) — disambiguation page
- Xinyi Zhang 0002
— Renmin University of China, China (and 1 more)
- Xinyi Zhang 0003 — University of California, Santa Barbara, CA, USA
- Xinyi Zhang 0004
- Xinyi Zhang 0005
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2020 – today
- 2022
- [j6]Sébastien Ollivier
Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge. IEEE Micro 42(6): 9-16 (2022) - [j5]Yue Tang
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization. ACM Trans. Design Autom. Electr. Syst. 27(5): 49:1-49:36 (2022) - [c6]Xinyi Zhang, Cong Hao, Peipei Zhou
H2H: heterogeneous model to heterogeneous system mapping with computation and communication awareness. DAC 2022: 601-606 - [i7]Yue Tang, Xinyi Zhang, Peipei Zhou, Jingtong Hu:
EF-Train: Enable Efficient On-device CNN Training on FPGA Through Data Reshaping for Online Adaptation or Personalization. CoRR abs/2202.10935 (2022) - [i6]Sébastien Ollivier, Xinyi Zhang, Yue Tang, Chayanika Choudhuri, Jingtong Hu, Alex K. Jones:
FPIRM: Floating-point Processing in Racetrack Memories. CoRR abs/2204.13788 (2022) - [i5]Xinyi Zhang, Cong Hao, Peipei Zhou, Alex K. Jones
H2H: Heterogeneous Model to Heterogeneous System Mapping with Computation and Communication Awareness. CoRR abs/2204.13852 (2022) - 2021
- [j4]Xiaowei Xu
DAC-SDC Low Power Object Detection Challenge for UAV Applications. IEEE Trans. Pattern Anal. Mach. Intell. 43(2): 392-403 (2021) - [j3]Xinyi Zhang, Yawen Wu, Peipei Zhou
Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices. ACM Trans. Embed. Comput. Syst. 20(5s): 71:1-71:24 (2021) - 2020
- [j2]Xinyi Zhang, Clay Patterson, Yongpan Liu, Chengmo Yang, Chun Jason Xue, Jingtong Hu
Low Overhead Online Data Flow Tracking for Intermittently Powered Non-Volatile FPGAs. ACM J. Emerg. Technol. Comput. Syst. 16(3): 26:1-26:20 (2020) - [c5]Xinyi Zhang, Weiwen Jiang, Jingtong Hu:
Achieving Full Parallelism in LSTM via a Unified Accelerator Design. ICCD 2020: 469-477 - [i4]Xinyi Zhang, Clay Patterson, Yongpan Liu, Chengmo Yang, Chun Jason Xue, Jingtong Hu:
Low Overhead Online Data Flow Tracking for Intermittently Powered Non-volatile FPGAs. CoRR abs/2002.02094 (2020)
2010 – 2019
- 2019
- [j1]Weiwen Jiang, Edwin H.-M. Sha, Xinyi Zhang, Lei Yang, Qingfeng Zhuge, Yiyu Shi, Jingtong Hu:
Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference. ACM Trans. Embed. Comput. Syst. 18(5s): 67:1-67:23 (2019) - [c4]Weiwen Jiang, Xinyi Zhang, Edwin Hsing-Mean Sha, Lei Yang, Qingfeng Zhuge, Yiyu Shi, Jingtong Hu:
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search. DAC 2019: 5 - [c3]Weiwen Jiang, Xinyi Zhang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Lei Yang, Yiyu Shi, Jingtong Hu:
XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI. FPGA 2019: 305 - [c2]Xinyi Zhang, Weiwen Jiang, Yiyu Shi, Jingtong Hu:
When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design. ISVLSI 2019: 25-30 - [i3]Weiwen Jiang, Xinyi Zhang, Edwin Hsing-Mean Sha, Lei Yang, Qingfeng Zhuge, Yiyu Shi, Jingtong Hu:
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search. CoRR abs/1901.11211 (2019) - [i2]Weiwen Jiang, Edwin Hsing-Mean Sha, Xinyi Zhang, Lei Yang, Qingfeng Zhuge, Yiyu Shi, Jingtong Hu:
Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference. CoRR abs/1907.08985 (2019) - 2018
- [c1]Xinyi Zhang, Clay Patterson, Yongpan Liu, Chengmo Yang, Chun Jason Xue, Jingtong Hu:
Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs. ISVLSI 2018: 238-244 - [i1]Xiaowei Xu, Xinyi Zhang, Bei Yu, Xiaobo Sharon Hu, Christopher Rowen, Jingtong Hu, Yiyu Shi:
DAC-SDC Low Power Object Detection Challenge for UAV Applications. CoRR abs/1809.00110 (2018)
Coauthor Index
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