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Hariharan Sankaran
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2010 – 2019
- 2011
- [j1]Hariharan Sankaran, Srinivas Katkoori
:
Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 217-226 (2011)
2000 – 2009
- 2009
- [c9]Hariharan Sankaran, Srinivas Katkoori
On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs. ISQED 2009: 33-39 - [c8]Hariharan Sankaran, Srinivas Katkoori
Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs. ISVLSI 2009: 274-279 - 2008
- [b1]Hariharan Sankaran:
High-Level Synthesis Framework for Crosstalk Minimization in VLSI ASICs. University of South Florida, Tampa, USA, 2008 - [c7]Didier Keymeulen, Adrian Stoica
Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications. AHS 2008: 83-90 - [c6]Hariharan Sankaran, Srinivas Katkoori
Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis. DELTA 2008: 454-457 - [c5]Didier Keymeulen, Adrian Stoica
Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core. ICES 2008: 225-236 - [c4]Pradeep Fernando, Hariharan Sankaran, Srinivas Katkoori
A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine. IPDPS 2008: 1-8 - [c3]Hariharan Sankaran, Srinivas Katkoori
Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis. ISVLSI 2008: 423-428 - 2005
- [c2]Hariharan Sankaran, Srinivas Katkoori
System Level Energy Optimization for Location Aware Computing. PerCom 2005: 319-323 - [c1]Suvodeep Gupta, Srinivas Katkoori
Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs. VLSI Design 2005: 463-468
Coauthor Index
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