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Hsin-I Wu
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2020 – today
- 2024
- [c16]You-En Wu, Hsin-I Wu, Kuo-Cheng Chin, Yi-Chun Yang, Ren-Song Tsay:
Accelerate Large Language Model Inference on Edge TPU with OpenVX framework. AICAS 2024: 502-506 - 2022
- [c15]Hsu-Hsun Chin, Ren-Song Tsay, Hsin-I Wu:
An Adaptive High-Performance Quantization Approach for Resource-Constrained CNN Inference. AICAS 2022: 336-339 - 2021
- [i4]Hsu-Hsun Chin, Ren-Song Tsay, Hsin-I Wu:
A High-Performance Adaptive Quantization Approach for Edge CNN Applications. CoRR abs/2107.08382 (2021) - [i3]Yun Chang, Hsin-I Wu, Ren-Song Tsay:
An Effective Parallel Program Debugging Approach Based on Timing Annotation. CoRR abs/2109.04142 (2021) - [i2]Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay:
Automatic Timing-Coherent Transactor Generation for Mixed-level Simulations. CoRR abs/2109.04148 (2021) - 2020
- [j2]Hsin-I Wu
, Da-Yi Guo, Ren-Song Tsay
A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent Interactions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5211-5224 (2020) - [c14]Hsin-I Wu, Da-Yi Guo, Hsu-Hsun Chin, Ren-Song Tsay:
A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems. AICAS 2020: 46-49 - [c13]Yin-Chun Ling, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay:
Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs. GCAIoT 2020: 1-7 - [c12]Kuo-Cheng Chin, Ren-Song Tsay, Hsin-I Wu:
A Heuristic Region-based Concurrency Bug Testing Approach. ISPA/BDCloud/SocialCom/SustainCom 2020: 1126-1135 - [c11]Hsin-I Wu, Ren-Song Tsay, Hsu-Hsun Chin:
VIRA: a virtualization assisted deterministic system-level simulations. SAC 2020: 596-598 - [c10]Hsin-I Wu, Ren-Song Tsay, Fong-Yuan Chang:
CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm. VLSI-DAT 2020: 1-4 - [i1]Tsung-Ying Lu, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay:
A Very Compact Embedded CNN Processor Design Based on Logarithmic Computing. CoRR abs/2010.11686 (2020)
2010 – 2019
- 2018
- [c9]Hsin-I Wu, Chi-Kang Chen, Tsung-Ying Lu, Ren-Song Tsay:
A highly efficient full-system virtual prototype based on virtualization-assisted approach. DATE 2018: 285-288 - 2017
- [c8]Yu-Lin Wei, Hsin-I Wu, Han-Chung Wang, Hsin-Mu Tsai, Kate Ching-Ju Lin, Rayana Boubezari, Hoa Le Minh
LiCompass: Extracting orientation from polarized light. INFOCOM 2017: 1-9 - 2016
- [c7]Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay:
An accurate and flexible early memory system power evaluation approach using a microcomponent method. CODES+ISSS 2016: 3:1-3:8 - [c6]Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay:
Poster Paper: An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. ICHI 2016: 304 - [c5]Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay:
An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. ICHI 2016: 456-460 - 2015
- [j1]Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak:
Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1822-1835 (2015) - [c4]Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay:
Automatic timing-coherent transactor generation for mixed-level simulations. ASP-DAC 2015: 588-593 - [c3]Hui-Yu Lee, Hao-Min Lin, Yu-Lin Wei, Hsin-I Wu, Hsin-Mu Tsai
RollingLight: Enabling Line-of-Sight Light-to-Camera Communications. MobiSys 2015: 167-180 - 2013
- [c2]Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee, Ren-Song Tsay:
A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations. DATE 2013: 643-648 - 2012
- [c1]Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay:
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation. DAC 2012: 127-132
Coauthor Index
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