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Microprocessors and Microsystems, Volume 71
Volume 71, November 2019
- Zhuqin Chu, Hui Li
, Huaxi Gu, Xiaochun Ye:
Wavelength assignment method based on ACO to reduce crosstalk for ring-based optical Network-on-Chip. - Arjun Kumar Joginipelly
Efficient separable convolution using field programmable gate arrays. - Weiwen Yu, Derek C. W. Pao:
Hardware accelerator for FIB lookup in named data networking. - Sambasivam Rajalakshmi, Parthasarathy Rangarajan:
Investigation of modified multilevel inverter topology for PV system. - Islam Gamal
A robust, real-time and calibration-free lane departure warning system. - Serwan Ali Bamerni
An efficient non-separable architecture for Haar wavelet transform with lifting structure. - Kwangho Lee, Joonho Kong, Young Geun Kim, Sung Woo Chung:
Memory streaming acceleration for embedded systems with CPU-accelerator cooperative data processing. - M. Mohamed Asan Basiri
LFSR based versatile divider architectures for BCH and RS error correction encoders. - V. M. Senthilkumar
A vedic mathematics based processor core for discrete wavelet transform using FinFET and CNTFET technology for biomedical signal processing. - Abraham Chavacheril Geevarghese, Madheswaran Muthusamy
FPGA implementation of IFFT architecture with enhanced pruning algorithm for low power application. - M. Prithivi Raj, G. Kavithaa:
Dynamic signal driving strategy based high speed and low powered dual edge triggered flip flop design used memory applications.
- K. B. Bavithra, R. Siva Kumar:
High throughput K best MIMO detector using modified final selector based carry select adder. - K. Ferents Koni Jiavana, S. Malarvizhi:
Lattice reduction aided pre-processor for large scale MIMO detection. - C. Kalamani
Design of Differential LNA and Double Balanced Mixer using 180 nm CMOS Technology. - P. Parthasaradhy, K. Manjunathachari
Accident avoidance and prediction system using adaptive probabilistic threshold monitoring technique. - J. K. Kasthuri Bha, P. Aruna Priya
Low power & high gain differential amplifier using 16 nm FinFET. - Zeynab Mohseni
Reliability characterization and activity analysis of lowRISC internal modules against single event upsets using fault injection and RTL simulation. - N. Mageswari, K. Mahadevan, R. Mohan Kumar:
An α-factor architecture for RS decoder implemented on 90 nm CMOS technology for computer computing applications devices. - R. Vijay Sai, Har Narayan Upadhyay
Undeviating Adaptive Sheltered Cryptography (UASC) method based low power and high secure cache memory design. - C. Puttamadappa, Parameshachari Bidare Divakarachari:
Demand side management of small scale loads in a smart grid using glow-worm swarm optimization technique. - K. Vasanth
VLSI architecture for Vasanth sorting to denoise image with minimum comparators. - M. Suaganthy, A. Karthikeyan
Investigation of turbo decoding techniques based on lottery arbiter in 3D network on chip. - C. Arun Prasath, C. Gowri Shankar
Voltage deviate-domino circuits for low power high-speed applications using prescient innovation model. - M. Sumalatha, P. V. Naganjaneyulu
Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising. - Sivakumar Arumugam, Premalatha Logamani:
Modeling and adaptive control of modified LUO converter. - K. Karthikeyan, S. K. Patnaik, Manickam Baskar
A dsPIC based optimal sizing of solar PV plant using ultra capacitors for transient power delivery. - K. Jamal, Kamsali Manjunatha Chari
Test pattern generation using thermometer code counter in TPC technique for BIST implementation. - S. Lekashri, P. Sakthivel:
Design and evaluation of dynamic partial reconfiguration using fault tolerance in asynchronous FPGA. - V. M. Senthilkumar
FINFET operational amplifier with low offset noise and high immunity to electromagnetic interference. - R. Venkatesan
Hyper spectral dimensionality reduction using hybrid discriminative local metric learning. - S. T. Mrudula, K. E. Srinivasa Murthy, M. N. Giri Prasad:
M-ABRC (Adaptive Binary Range Coder) using Virtual Sliding Window technique and its VLSI implementation.
- Andrey Sadovykh
On a tool-supported model-based approach for building architectures and roadmaps: The MegaM@Rt2 project experience. - Gagandeep Singh, Lorenzo Chelini, Stefano Corda
Near-memory computing: Past, present, and future.
- Petr Socha
Efficient algorithmic evaluation of correlation power analysis: Key distinguisher based on the correlation trace derivative. - Markku Vajaranta, Arto Oinonen
Feasibility of FPGA accelerated IPsec on cloud. - Victor Arribas
Guards in action: First-order SCA secure implementations of KETJE without additional randomness. - Johan Laurent, Vincent Beroulle, Christophe Deleuze, Florian Pebay-Peyroula, Athanasios Papadimitriou
Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor. - Niels Pirotte, Jo Vliegen, Lejla Batina, Nele Mentens
Balancing elliptic curve coprocessors from bottom to top. - Sébastien Carré, Matthieu Desjardins, Adrien Facon, Sylvain Guilley:
Exhaustive single bit fault analysis. A use case against Mbedtls and OpenSSL's protection on ARM and Intel CPU. - Nikolaos Athanasios Anagnostopoulos
Attacking SRAM PUFs using very-low-temperature data remanence. - Krishnendu Guha, Atanu Majumder, Debasri Saha, Amlan Chakrabarti
Criticality based reliability against hardware Trojan attacks for processing of tasks on reconfigurable hardware. - Apostolos P. Fournaris
An efficient multi-parameter approach for FPGA hardware Trojan detection.
- Lorenzo Servadei, Elena Zennaro, Tobias Fritz, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille:
Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications. - Wangsheng Yu
Deep discriminative correlation tracking based on adaptive feature fusion. - Emanuele Torti
Embedding Recurrent Neural Networks in Wearable Systems for Real-Time Fall Detection.
- Bernhard Jungk, Marc Stöttinger
Serialized lightweight SHA-3 FPGA implementations.
- Xinhui Lai, Aneesh Balakrishnan
Understanding multidimensional verification: Where functional meets non-functional. - Morten B. Petersen, Anthon V. Riber, Simon T. Andersen, Martin Schoeberl
Time-predictable distributed shared on-chip memory.
- Leonardo Suriano
DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping. - D. Kalaiyarasi, T. Kalpalatha Reddy:
Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic.
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