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Integration, Volume 4
Volume 4, Number 1, March 1986
- Lambert Spaanenburg:
Editorial. 1 - John C. Peterson, Kent F. Smith:
MASHER: An automatic VLSI layout system. 3-33 - Morris Balamut, Ed Kinnen, Rosanne Wyleczuk:
SPICE Rack - the newsletter of the SPICE users group : Volume 4, number 1, fall 1985. 35-41 - J. S. T. Huang, J. M. Daughton:
Yield optimization in wafer scale circuits with hierarchical redundancies. 43-51 - William F. Clocksin, Miriam Leeser
:
Automatic determination of signal flow through MOS transistor networks. 53-63 - Hans-Werner Lang:
The instruction systolic array - a parallel architecture for VLSI. 65-74 - Christer Svensson:
Signal resynchronization in VLSI systems. 75-80
Volume 4, Number 2, June 1986
- Lambert Spaanenburg:
Editorial. 97 - Tam-Anh Chu:
On the models for designing VLSI asynchronous digital systems. 99-113 - Hiroshi Miyashita, Tohru Adachi, Kazuhiro Ueda:
An automatic cell pattern generation system for CMOS transistor-pair array LSI. 115-133 - Cheng T. Wang:
VLSI architecture for device simulation. 135-153 - Evert Dijkstra, Christian Piguet:
On minimizing memory in systolic arrays for the dynamic time warping algorithm. 155-173 - Howard C. Card, Werner Pries, Robert D. McLeod:
Contributions to VLSI computational complexity theory from bounds on current density. 175-183 - J. G. Rathmell:
Information flow in VLSI design. 185-191 - Philippe De Wilde:
The SPIRIT of ESPRIT. 193 - H. Groen:
"X/OPEN Portability Guide" by the X/OPEN Group, from: Elsevier SciencePublishers B.V., Book Order Department, P.O. Box 211, 1000 AE Amsterdam, The Netherlands. 195 - M. Bergman:
"Introduction to nMOS and cMOS VLSI Systems Design" by Amar Mukherjee, from: Prentice-Hall, Englewood Cliffs, NJ 07632, U.S.A.. 195-196
Volume 4, Number 3, September 1986
- Emile H. L. Aarts, Frans M. J. de Bont, Erik H. A. Habers, Peter J. M. van Laarhoven:
Parallel implementations of the statistical cooling algorithm. 209-238 - L. G. Chen, Jau-Yien Lee, Jhing-Fa Wang, K. T. Chen:
Fast execution for circuit consistency verification. 239-262 - Magdy A. Bayoumi:
Lower bounds for VLSI implementation of residue number system architectures. 263-269 - Bruce W. Char:
Computer algebra and logic programming. 271-274
Volume 4, Number 4, December 1986
- Lambert Spaanenburg:
Editorial. 285 - D. F. Wong
Compacted channel routing with via placement restrictions. 287-307 - Thomas Lengauer, Stefan Näher:
An analysis of ternary simulation as a tool for race detection in digital MOS circuits. 309-330 - Sergio Cesare Brofferio, Michele Taliercio:
PLA implementation of a differential predictive coder for digital television signals. 331-343 - Salim U. Chowdhury, Melvin A. Breuer:
An O(n) algorithm for width determination of power/ground routes for VLSI circuits. 345-355
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