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IEEE Design & Test of Computers, Volume 7
Volume 7, Number 1, January-February 1990
- D&T News. IEEE Des. Test Comput. 7(1): 2, 5 (1990)
- Editorial Calendar. IEEE Des. Test Comput. 7(1): 4- (1990)
- Ben Bennetts:
Test Technology in Europe. IEEE Des. Test Comput. 7(1): 6-8 (1990) - R. P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg:
Designing and Implementing an Architecture with Boundary Scan. 9-19 - Hugu K. Seitz, Armin Blacha, Rolf Clauberg
, H. Beha, J. Feder:
Contactless High-Speed Waveform Measurements on Gallium. 20-25 - Phil Nigh, Wojciech Maly:
Test Generation for Current Testing (CMOS ICs). 26-38 - Bas Verhelst:
Using a Test-Specification Format in Automatic Test-Program Generation. 39-45 - The Challenges of Self-Test. IEEE Des. Test Comput. 7(1): 46-54 (1990)
- A D&T Roundtable: Behavioral Description Languages, Part 1: Are Designers Benefitting? IEEE Des. Test Comput. 7(1): 56-62 (1990)
- The 1989 Annual Index. IEEE Des. Test Comput. 7(1): 63-67 (1990)
- DATC Newsletter. IEEE Des. Test Comput. 7(1): 70-71 (1990)
Volume 7, Number 2, March-April 1990
- M. Ray Mercer:
Guest Editorial: ITC 20th Anniversary. IEEE Des. Test Comput. 7(2): 2-3 (1990) - Christopher W. Branson:
Integrating Tester Pin Electronics. 4-14 - Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick, Donald L. Wheater:
Low-Cost Testing of High-Density Logic Components. 15-28 - Richard Illman, Stephen Clarke:
Built-In Self-Test of the Macrolan Chip. 29-40 - Frans P. M. Beenker, Barry J. Dekker, Richard Stans, Max van der Star:
Implementing Macro Test in Silicon Compiler Design. 41-51 - Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal:
Serial Interfacing for Embedded-Memory Testing. 52-63 - A D&T Roundtable: Behavioral Description Languages, Part 2: VHDL vs. UDL/I. IEEE Des. Test Comput. 7(2): 64-68 (1990)
- TTTC Newsletter. IEEE Des. Test Comput. 7(2): 70-71 (1990)
Volume 7, Number 3, May-June 1990
- D&T News. IEEE Des. Test Comput. 7(3): 2, 4, 6-7, 64 (1990)
- James R. Armstrong:
Tuning VHDL for Multivalve Logic Modeling. IEEE Des. Test Comput. 7(3): 8-10 (1990) - Paul J. Menchini:
A Minimalist Approach to VHDL Logic Modeling. 12-23 - David R. Coelho:
A VHDL Standard Package for Logic Modeling. 25-32 - Steven P. Smith, Ramón D. Acosta:
A Value System for Switch-Level Modeling. 33-41 - Joanne DeGroat:
Transparent Logic Modeling in VHDL. 42-48 - Alfred S. Gilman:
Logic Modeling in WAVES. 49-55 - A D&T Roundtable: Does VLSI Education Meet Industry's Needs?. IEEE Des. Test Comput. 7(3): 56-63 (1990)
- DATC Newsletter. IEEE Des. Test Comput. 7(3): 70-71 (1990)
Volume 7, Number 4, July-August 1990
- D&T News. IEEE Des. Test Comput. 7(4): 2-3, 76 (1990)
- Kenneth D. Wagner:
Guest Editorial: The Many Faces of Test. IEEE Des. Test Comput. 7(4): 4- (1990) - Sandip Kundu, Sudhakar M. Reddy:
Embedded Totally Self-Checking Checkers: A Practical Design. 5-12 - David A. Wood, Garth A. Gibson
Verifying a Multiprocessor Cache Controller Using Random Test Generation. 13-25 - Kewal K. Saluja, Kyuchull Kim:
Improved Test Generation for High-Activity Circuits. 26-31 - Vishwani D. Agrawal, Hatsuyoshi Kato:
Fault Sampling Revisited. 32-35 - Afaq Ahmad
Are Primitive Polynomials Always Best in Signature Analysis? 36-38 - Sakti P. Ghosh, Edward G. Grochowski:
Dynamic Statistical Control of Manufacturing Test. 39-51 - Jer-Min Jou, Jau-Yien Lee, Yachyang Sun, Jhing-Fa Wang:
An Efficient VLSI Switch-Box Router. 52-65 - A D&T Roundtable: System Test-What, Why, and How? IEEE Des. Test Comput. 7(4): 66-72 (1990)
- TTTC Newsletter. IEEE Des. Test Comput. 7(4): 78-79 (1990)
Volume 7, Number 5, September-October 1990
- D&T News. IEEE Des. Test Comput. 7(5): 3-4 (1990)
- Giovanni De Micheli:
Guest Editorial: High-Level Synthesis of Digital Circuits. IEEE Des. Test Comput. 7(5): 6-7 (1990) - Raul Camposano:
From Behavior to Structure: High-Level Synthesis. 8-19 - Jayaram Bhasker, Huan-Chih Lee:
An Optimizer for Hardware Synthesis. 20-36 - Giovanni De Micheli, David C. Ku, Frédéric Mailhot, Thomas K. Truong:
The Olympus Synthesis System. 37-53 - Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong:
Neural Net and Boolean Satisfiability Models of Logic Circuits. 54-57
- DATC Newsletter. IEEE Des. Test Comput. 7(5): 62-63 (1990)
Volume 7, Number 6, November-December 1990
- D&T News. 5-7, 41
- What's Ahead for 1991? IEEE Des. Test Comput. 7(6): 2-3 (1990)
- Nikil D. Dutt
Design Synthesis and Silicon Compilation. 8-23 - Jung-Gen Wu, Yu Hen Hu, William P.-C. Ho, David Y. Y. Yun:
A Model-Based Expert System for Digital System Design. 24-40 - Peter M. Maurer:
Dynamic Functional Testing for VLSI Circuits. 42-49 - A D&T Roundtable: Synthesis for Testability. IEEE Des. Test Comput. 7(6): 50-59 (1990)
- 1990 Annual Index. IEEE Des. Test Comput. 7(6): 60-65 (1990)
- TTTC Newsletter. IEEE Des. Test Comput. 7(6): 70-71 (1990)
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