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IEEE Computer Architecture Letters, Volume 15
Volume 15, Number 1, January - June 2016
- Wo-Tak Wu, Ahmed Louri:
A Methodology for Cognitive NoC Design. 1-4 - Seyyed Hossein Seyyedaghaei Rezaei, Abbas Mazloumi, Mehdi Modarressi, Pejman Lotfi-Kamran:
Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip. 5-8 - Miguel Gorgues, José Flich
:
End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance. 9-12 - Biswabandan Panda, Shankar Balachandran:
Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers. 13-16 - Abdulaziz Eker, Oguz Ergin
Exploiting Existing Copies in Register File for Soft Error Correction. 17-20 - Matthew Maycock, Simha Sethumadhavan:
Hardware Enforced Statistical Privacy. 21-24 - Dongdong Li, Tor M. Aamodt:
Inter-Core Locality Aware Memory Scheduling. 25-28 - Libei Pu, Kshitij A. Doshi, Ellis Giles, Peter J. Varman
Non-Intrusive Persistence with a Backend NVM Controller. 29-32 - Paulo Garcia
On-Chip Message Passing Sub-System for Embedded Inter-Domain Communication. 33-36 - Minghua Li, Guancheng Chen, Qijun Wang, Yonghua Lin, H. Peter Hofstee, Per Stenström, Dian Zhou:
PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor. 37-40 - Mohammad Alian
pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems. 41-44 - Yoongu Kim, Weikun Yang, Onur Mutlu:
Ramulator: A Fast and Extensible DRAM Simulator. 45-49 - Lena E. Olson
Security Implications of Third-Party Accelerators. 50-53 - Bruce L. Jacob:
The Case for VLIW-CMP as a Building Block for Exascale. 54-57 - Marios Kleanthous, Yiannakis Sazeides, Emre Özer, Chrysostomos Nicopoulos
Toward Multi-Layer Holistic Evaluation of System Designs. 58-61 - Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan:
Towards High-Performance Bufferless NoCs with SCEPTER. 62-65
Volume 15, Number 2, July - December 2016
- Shuang Liang, Shouyi Yin, Leibo Liu
A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. 69-72 - Bo-Cheng Charles Lai, Luis Garrido Platero, Hsien-Kai Kuo:
A Quantitative Method to Data Reuse Patterns of SIMT Applications. 73-76 - Yaman Cakmaki, Will Toms, Javier Navaridas
Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling. 77-80 - Erik Tomusk, Christophe Dubach:
Diversity: A Design Goal for Heterogeneous Processors. 81-84 - Milad Hashemi, Debbie Marr, Doug Carmean, Yale N. Patt:
Efficient Execution of Bursty Applications. 85-88 - Sudarsun Kannan
Energy Aware Persistence: Reducing the Energy Overheads of Persistent Memory. 89-92 - Alejandro Valero
Enhancing the L1 Data Cache Design to Mitigate HCI. 93-96 - Rathijit Sen, David A. Wood:
GPGPU Footprint Models to Estimate per-Core Power. 97-100 - Daejin Jung, Sheng Li, Jung Ho Ahn
Large Pages on Steroids: Small Ideas to Accelerate Big Memory Applications. 101-104 - Javier Verdú
Performance Scalability Analysis of JavaScript Applications with Web Workers. 105-108 - Christina Delimitrou, Christos Kozyrakis:
Security Implications of Data Mining in Cloud Scheduling. 109-112 - Zhenning Wang, Jun Yang, Rami G. Melhem, Bruce R. Childers, Youtao Zhang, Minyi Guo:
Simultaneous Multikernel: Fine-Grained Sharing of GPUs. 113-116 - Chulian Zhang
Studying Inter-Warp Divergence Aware Execution on GPUs. 117-120 - Arash Tavakkol
TBM: Twin Block Management Policy to Enhance the Utilization of Plane-Level Parallelism in SSDs. 121-124 - Bruce L. Jacob:
The 2 PetaFLOP, 3 Petabyte, 9 TB/s, 90 kW Cabinet: A System Architecture for Exascale and Big Data. 125-128 - He Xiao, Wen Yueh, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures. 129-132 - Qi Hu, Peng Liu
Threads and Data Mapping: Affinity Analysis for Traffic Reduction. 133-136
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