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28th VLSI-SOC 2020: Salt Lake City, UT, USA
- 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020. IEEE 2020, ISBN 978-1-7281-5409-1
- Andrew B. Kahng:
Open-Source EDA: If We Build It, Who Will Come? 1-6 - Luca P. Carloni
:
Scalable Open-Source System-on-Chip Design: (Invited Talk - Extended Abstract). 7-9 - Justin Morris
Multi-label HD Classification in 3D Flash. 10-15 - Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. 16-21 - Yukio Miyasaka, Masahiro Fujita:
SAT-Based Data-Flow Mapping Onto Array Processor. 22-27 - Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. 28-33 - Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. 34-39 - Xiaoyu Lian, Sherief Reda, Jacob K. Rosenstein:
Simultaneous Estimation of Temperature and Voltage from Digital Delay Diversity. 40-45 - S. Moraitis, D. Seitanidis, George Theodoridis, Odysseas G. Koufopavlou:
Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein Ciphers. 46-51 - David Cordova, Wim Cops, Yann Deval, Francois Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin:
A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOI. 52-57 - Alessandro Veronesi
Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator. 58-63 - Natan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. 64-69 - Siddhartha Chowdhury, Debapriya Basu Roy, Debdeep Mukhopadhyay:
A Minimalistic Perspective on Koblitz Curve Scalar Multiplication for FPGA Platforms. 70-75 - Chhandak Mukherjee, Marina Deng
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. 76-81 - Tannu Sharma, Kenneth S. Stevens:
Automatic Timing Closure for Relative Timed Designs. 82-87 - Mayank Rawat
Mining Hyperproperties from Behavioral Traces. 88-93 - William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza:
A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance. 94-99 - Amin Aghighi, Massood Tabib-Azar, Armin Tajalli:
An ULP Self-Supplied Brain Interface Circuit. 100-104 - Amin Aghighi, Behrouz Farhang-Boroujeny
Energy and Area Efficient Mixed-Mode MCMC MIMO Detector. 105-110 - Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli
MIST: monitor generation from informal specifications for firmware verification. 111-116 - Michail Moraitis
Breaking ACORN at Bitstream Level. 117-122 - Brian Crafton, Samuel Spetalnick, Gauthaman Murali
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. 123-128 - Yinghua Hu
SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption Scheme. 129-134 - Love Kumar Sah, Srivarsha Polnati, Sheikh Ariful Islam, Srinivas Katkoori
Basic Block Encoding Based Run-time CFI Check for Embedded Software. 135-140 - Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala
An Open-source Framework for Autonomous SoC Design with Analog Block Generation. 141-146 - Samiran Ganguly, Nikhil Shukla, Avik W. Ghosh:
Ultra-Compact, Scalable, Energy-Efficient $VO_{2}$ Insulator-Metal-Transition Oxide Based Spiking Neurons for Liquid State Machines. 147-152 - Josie E. Rodriguez Condia
Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy. 153-158 - Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury:
A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. 159-164 - Jonas Gava
RAT: A Lightweight System-level Soft Error Mitigation Technique. 165-170 - Amin Aghighi, Armin Tajalli, Mohammad Taherzadeh-Sani:
A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. 171-175 - Yongnan Chen, Yanhan Zeng, Junkai Chen, Hong-Zhou Tan:
PT controlled buck converter with adaptive PCCM using charge monitoring and NMOS current sensing. 176-180 - Haochang Zhi
Fast-transient, light-load efficient DC-DC converter using an auxiliary D-LDO. 181-185 - Matthias Eberlein, Harald Pretl
Subthreshold-Hybrid Solutions for Thermal Sensor and Reference Circuits in Advanced CMOS. 186-191 - Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein:
Temperature and Supply Voltage Monitoring with Current-mode Relaxation Oscillators. 192-197 - N. Nalla Anandakumar, Somitra Kumar Sanadhya, Mohammad S. Hashmi
Design, Implementation and Analysis of Efficient Hardware-Based Security Primitives. 198-199 - Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur:
Multiple-NoC Exploration and Customization for Energy Efficient Traffic Distribution. 200-201 - Rajat Sadhukhan, Debdeep Mukhopadhyay:
Design Automation for Side Channel Resistant Lightweight Cryptography. 202-203 - Valentino Peluso, Enrico Macii, Andrea Calimera:
Optimization Tools for ConvNets on the Edge. 204-205 - Foroozan Karimzadeh, Arijit Raychowdhury:
Memory and Energy Efficient Method Toward Sparse Neural Network Using LFSR Indexing. 206-207 - Ashwin Sanjay Lele, Yan Fang, Justin Ting, Arijit Raychowdhury:
Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod Locomotion. 208-209 - Xuan Hu, Naimul Hassan, Wesley H. Brigner, Maverick Chauwin, Joseph S. Friedman:
Device Modeling and Circuit Design for Scalable Beyond-CMOS Computing. 210-211
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