default search action
SoCC 2013: Erlangen, Germany
- Norbert Schuhmann, Kaijian Shi, Nagi Naganathan:
2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013. IEEE 2013, ISBN 978-1-4799-1166-0 - Norbert Schuhmann:
Message from conference general chair. 4-5 - Kaijian Shi, Nagi Naganathan:
Message from program chairs. 6 - Ronald M. Martino:
Keynote speaker: "The roadway to innovation". 29 - Carsten Elgert:
Plenary speaker: "The pig in the poke? - Strategies to avoid unpleasant surprises with IP on your SoC". 30 - Volker Politz:
Plenary speaker: "Visions of future SoC design: Why heterogeneous architectures and power matter". 31 - Po-Yen Chiu, Ming-Dou Ker:
Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology. 33-36 - Lafifa Jamal
, Md. Mushfiqur Rahman, Hafiz Md. Hasan Babu:
An optimal design of a fault tolerant reversible multiplier. 37-42 - Esraa Swillam, Kareem Madkour, Mohab Anis:
Layout regularity metric as a fast indicator of high variability circuits. 43-48 - Yu-Long Huang, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu
Architecture and circuit design of parallel processing elements for de novo sequence assembly. 50-54 - Xiaolu Guo, Mario R. Casu
UWB receiver for breast cancer detection: Comparison between two different approaches. 55-60 - Dung Nguyen, Kui Ren
A new data acquisition design for breast cancer detection system. 61-66 - Young-Ho Kim, Sang-Soo Lee:
A 72dBO 11.43mA novel CMOS regulated cascode TIA for 3.125Gb/s optical communications. 68-72 - Yanqiu Huang
PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor Networks. 73-78 - Sheng-Kai You, Po-Hsuan Chang
A 6Gb/s 40dB burst-mode digitally adaptive equalizer with reference-calibrated overshoot control. 79-82 - Sushrant Monga:
Adaptive driver with automatic sense and calibration in CMOS 40LP. 83-86 - Heinrich Milosiu, Frank Oehler:
Sub-10 µW CMOS wake-up receiver IP for green SoC designs. 88-91 - Mei-Wei Chen, Ming-Hung Chang, Pei-Chen Wu, Yi-Ping Kuo, Chun-Lin Yang, Yuan-Hua Chu, Wei Hwang:
A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. 92-97 - Hafiz Md. Hasan Babu, Lafifa Jamal
An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder. 98-103 - Nan-Chun Lien, Ching-Te Chuang, Wen-Rong Wu:
Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation. 105-109 - Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu:
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. 110-115 - Jens Spinner, Jürgen Freudenberger
A BCH decoding architecture with mixed parallelization degrees for flash controller applications. 116-121 - Martin Krey, Daniel Sabotta, Fabian Zahn, Karl-Ragmar Riemschneider
Development of advanced diagnostic functions in very high volume automotive sensor applications. 123-128 - Shih-Chieh Fan Chiang, Po-Hsiang Hsu, Yi-Chang Lu
Light field data processor design for depth estimation using confidence-assisted disparities. 129-133 - Chun-Liang Kuo, Yang-Yao Lin, Yi-Chang Lu
Analysis and implementation of Discrete Wavelet Transform for compressing four-dimensional light field data. 134-138 - Jürgen Herre:
Banquet speaker: "The MP3 story and more: Perceptual audio coding from its beginnings to the present". 139 - Taewhan Kim:
Tutorial: Methodology for designing reliable clock networks. 141 - Andrew Marshall, Karan S. Bhatia:
Tutorial: The uncertain end to silicon. 143 - Bill Huffman:
Plenary speaker: "Processor-to-memory interface design methodologies for energy and performance efficiencies". 145 - Goro Suzuki:
Multiple terminal reduction method. 147-152 - Byunghyun Lee, Taewhan Kim:
High-level TSV resource sharing and optimization for TSV based 3D IC designs. 153-158 - Chia-Hung Liu, Kuang-Cheng Liu, Juinn-Dar Huang
Latency-optimization synthesis with module selection for digital microfluidic biochips. 159-164 - Lufei Shen, Klaus Hofmann:
Advanced clock schemes with dead time techniques for high voltage charge pumps. 166-171 - Shani Rehana, Or Turgeman, Ran Manevich, Avinoam Kolodny:
ViLoCoN - An ultra-lightweight lossless VLSI video codec. 172-177 - Prakash Krishnamoorthy, Ramesh C. Tekumalla:
Power aware transformation of bandlimited signals. 178-183 - Ballori Banerjee, Jim Vomero:
Treat thy secondary (ALMOST) like thy primary- A fair arbiter in master-slave configuration. 184-190 - Ashok Jaiswal, Yuan Fang, Kashif Nawaz
A wide range programmable duty cycle corrector. 192-196 - Chun-Chieh Chiu, Chih-Hsing Lin, Chih-Chyau Yang, Yi-Jun Liu, Ssu-Ying Chen, Jin-Ju Chue, Chih-Ting Kuo, Gang-Neng Sung, Chun-Pin Lin, Chien-Ming Wu, Chun-Ming Huang:
Morpack Cube: A portable 3D heterogeneous system integration platform. 197-202 - Mazen El Maraghy, Salma Hesham, Mohamed A. Abd El Ghany
Real-time efficient FPGA implementation of aes algorithm. 203-208 - Chun-Jen Wei, Yi-Yao Weng, Wen-Chung Tsai, Sao-Jie Chen
Novel time-multiplexing bidirectional on-chip network. 210-215 - Ayman A. Salem, Mohamed A. Abd El-Ghany
Coding algorithms for network on a chip. 216-221 - Tung Nguyen
High-performance adaption of ARM processors into Network-on-Chip architectures. 222-227 - Jonathan Young:
Plenary speaker: "Power-centric timing optimization for low power CPU hardening". 229 - Janet Roveda, Dung Nguyen, Linda S. Powers, Kui Ren
Effective signal region based analog mixed signal design considering variations and applications. 233-238 - Chorng-Sii Hwang, Ting-Li Chu, Po-Hsun Chen:
DLL-based programmable clock multiplier using differential toggle-pulsed latch. 239-243 - Sergey G. Mosin
Design-for-testability automation of mixed-signal integrated circuits. 244-249 - Prashanth Srinivasa:
Scalable system map library for address map and data integrity verification. 250-255 - Tanvir Ahmed, Ankur Sarker, Mohd. Istiaq Sharif, S. M. Mahbubur Rashid
A novel approach to design a reversible shifter circuit using DNA. 256-261 - Hiroyuki Ochi, Toshihiko Ota, Ataru Yamaoka, Hiromasa Watanabe, Yohei Kondo, Nobuyuki Tokuda, Hiroyuki Taguchi, Taketoshi Matsumoto, Tomoki Akai, Hikaru Kobayashi, Shigeki Imai:
Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation. 262-266 - Ali Sayyed
Implementation and performance analysis of variable latency adders. 267-272 - Prakash Krishnamoorthy, Ramesh C. Tekumalla:
Quotient prediction for low power division. 273-277 - Kaijian Shi:
Sleep transistor design in 28nm CMOS technology. 278-283 - Olivier Nasrallah, Wolfram Luithardt, Daniel Rossier, Alberto Dassatti
SOSoC, a Linux framework for System Optimization using System on Chip. 284-289 - Davide Zoni
An analytical, dynamic, power-performance router model for run-time NoC optimizations. 290-295 - Philipp Wehner, Max Ferger, Diana Göhringer, Michael Hübner:
Rapid prototyping of a portable HW/SW co-design on the virtual zynq platform using SystemC. 296-300 - Alexander Biedermann, Boris Dreyer
A generic, scalable reconfiguration infrastructure for sensor networks functionality adaption. 301-306 - Jung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez:
A formalism of the specifications for library development. 307-312 - Roman P. Bazylevych, Lubov Bazylevych:
Tutorial: Macro-modeling for solving SOC physical design automation problems. 314 - Tsung-Yi Ho
Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration. 316-317 - Yuan Fang, Ashok Jaiswal, Klaus Hofmann:
Low-power signal integrity trainings for multi-clock source-synchronous memory systems. 319-324 - Chien-Yu Lu, Ching-Te Chuang:
A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance. 325-329 - Gerard M. Blair:
Equal length routing. 331-335 - Cristian E. Onete
Finding ground traces using the laplacian of the meshes of the associated graph. 336-341 - Seung Mo Jung, Jong Hyun Seok, Ho Jin Yoo, Do Hyung Kim, You Keun Han, Woo-Seop Kim, Joo-Sun Choi, Jun Dong Cho
Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module. 343-348 - Salim Farah, Magdy A. Bayoumi:
A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic. 349-354 - Venkat Krishnan Balasubramanian, Hao Xu, Ranga Vemuri
Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuits. 355-360 - Naseef Mansoor, Manoj Prashanth Yuvaraj, Amlan Ganguly:
A robust medium access mechanism for millimeter-wave Wireless Network-on-Chip architecture. 362-367 - Ruizhe Wu, Dan Zhao:
Integrated routing and channel arbitration in overlaid mesh WiNoC. 368-373 - Changlin Chen, Sorin Dan Cotofana
A low cost method to tolerate soft errors in the NoC router control plane. 374-379
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-07-19 02:21 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: