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29th SBCCI 2016: Belo Horizonte, Brazil
- 29th Symposium on Integrated Circuits and Systems Design, SBCCI 2016, Belo Horizonte, Brazil, August 29 - September 3, 2016. IEEE 2016, ISBN 978-1-5090-2736-1
- Wolfgang Schreiber-Prillwitz, Reinhart Job:
Development process for MEMS pressure sensors for standarized CMOS read-out circuitry. 1-6 - Gustavo Sanchez
, Luciano Volcan Agostini
Energy-aware light-weight DMM-1 patterns decoders with efficiently storage in 3D-HEVC. 1-6 - Hiroyuki Yamauchi
A mutual rectification-interference avoidance technique with cascade filters for both downward-direction tailed-RDF deconvolution. 1-6 - Guilherme M. Castilhos, Fernando Gehm Moraes
A lightweight software-based runtime temperature monitoring model for multiprocessor embedded systems. 1-6 - Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos
Evaluating the impact of circuit legalization on incremental optimization techniques. 1-6 - Arturo Fajardo Jaimes
Modeling and design of high-efficiency power amplifiers fed by limited power sources. 1-6 - Arturo Fajardo Jaimes
Integrated CMOS class-E power amplifier for self-sustaining wireless power transfer system. 1-6 - Fábio Luís Livi Ramos, Jones Goebel, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi
Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos. 1-6 - David Cordova, Arthur Campos de Oliveira, Pedro Toledo, Hamilton Klimach, Sergio Bampi
A 0.3 V, high-PSRR, picowatt NMOS-only voltage reference using zero-VT active loads. 1-6 - Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans
A standard cell characterization flow for non-standard voltage supplies. 1-6 - Felipe Todeschini Bortolon, Sergio Johann Filho, Matheus Gibiluka, Sergio Bampi
Design and analysis of the HF-RISC processor targeting voltage scaling applications. 1-6 - Alyson Trindade, Ricardo S. Ferreira, José Augusto Miranda Nacif, Douglas Sales, Omar P. Vilela Neto
A Placement and routing algorithm for Quantum-dot Cellular Automata. 1-6 - Leonardo Bandeira Soares, Cláudio Machado Diniz, Eduardo Antonio Cesar da Costa
A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding. 1-6 - Rodrigo Cataldo, Guilherme Korol, Ramon Fernandes, Debora Matos, César A. M. Marcon
Architectural exploration of Last-Level Caches targeting homogeneous multicore systems. 1-6 - Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Martha Johanna Sepúlveda:
Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack. 1-6 - Felipe Piovezan, Tarcisio E. M. Crocomo, Luiz C. V. dos Santos
Cache sizing for low-energy Elliptic Curve Cryptography. 1-6 - Felipe Gohring de Magalhaes, Fabiano Hessel
Cluster-based architecture relying on Optical Integrated Networks with the provision of a low-latency arbiter. 1-6 - Ramon Fernandes, César A. M. Marcon
A security aware routing approach for NoC-based MPSoCs. 1-6 - Raphael Martins Brum, Gilson I. Wirth
MagPDK: An open-source process design kit for circuit design with magnetic tunnel junctions. 1-6 - Oscar Anacona-Mosquera, Janier Arias-Garcia
Efficient hardware implementation of the Richardson-Lucy Algorithm for restoring motion-blurred image on reconfigurable digital system. 1-6 - Frederique Simbelie, Sylvain Laurent, Pierre Medrel
Characterization and nonlinear modeling of MASMOS® transistor in order to design power amplifiers for LTE applications. 1-6 - Fernanda D. V. R. Oliveira, Tiago M. de F. Lopes, José Gabriel Rodríguez Carneiro Gomes, Fernando Antonio Pinto Barúqui, Antonio Petraglia:
Focal-plane image encoder with cascode current mirrors and increased vector quantization bit rate. 1-6 - Francois Rivet
An ultra wide band analog-to-digital converter based on a Delta-Riemann architecture. 1-4 - Yann Deval
A balanced logic routing block for Factorial-DLL based Frequency Generation. 1-4 - Ademir Marques Jr., Alexandro Baldassin
Energy-aware scheduling in transactional memory systems. 1-6 - Mateus Melo, Gustavo H. Smaniotto, Henrique Maich, Luciano Volcan Agostini
A parallel Motion Estimation solution for heterogeneous System on Chip. 1-6 - Mateus S. Oliveira, Paulo César Comassetto de Aguirre
A digitally tunable 4th-order Gm-C low-pass filter for multi-standards receivers. 1-6 - Pierre Bisiaux, Caroline Lelandais-Perrault
A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor. 1-6 - Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet:
New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. 1-6 - André F. Ponchet, Ezio M. Bastida, Celio Finardi, Roberto R. Panepucci
A design methodology for low-noise CMOS transimpedance amplifiers based on shunt-shunt feedback topology. 1-6 - Arthur Liraneto Torres Costa, Hamilton Klimach, Sergio Bampi
A 450 mV supply self-biased wideband inductorless balun LNA for sub-GHz applications. 1-6 - Antonyus Pyetro do Amaral Ferreira, Joao G. M. Silva, Jefferson R. L. Anjos, Luiz H. A. Figueiroa, Edna Natividade da Silva Barros
A hardware accelerator for the alignment of multiple DNA sequences. 1-6 - Rafael B. Schivittz, Rafael Fritz, Denis Teixeira Franco, Lirida A. B. Naviner
Inserting permanent fault input dependence on PTM to improve robustness evaluation. 1-6 - Erika S. Albuquerque, Antonyus Pyetro do Amaral Ferreira, Joao G. M. Silva, João Paulo Fernandes Barbosa, Renato L. M. Carlos, Djeefther S. Albuquerque, Edna Natividade da Silva Barros
An FPGA-based accelerator for multiple real-time template matching. 1-6 - E. Petitprez, Dalton M. Colombo
Successful prototyping of complex integrated circuits with focused ion beam. 1-5 - Mario Vinicius Guimaraes, Frank Sill Torres
Automatic layout integration of Bulk Built-In Current Sensors for detection of soft errors. 1-6 - Fabian Olivera
Analytic boundaries for 6T-SRAM design in standby mode. 1-6 - Pedro Toledo, Rene Timbo, David Cordova, Hamilton Klimach, Sergio Bampi
A 0.7V Fully Differential First Order GZTC-C filter. 1-6 - Eduardo Lussari, Duarte Lopes de Oliveira, Lester de Abreu Faria, Orlando Verducci Jr.:
Software-Defined Radio design based on GALS architecture for FPGAs. 1-6 - Andres Amaya, Héctor Gómez, Elkim Roa
A digital offset correction method for high speed analog front-ends. 1-4
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