default search action
ISVLSI 2008: Montpellier, France
- IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France. IEEE Computer Society 2008, ISBN 978-0-7695-3170-0
Keynotes
- Jürgen Becker:
Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era. 1-2 - Christophe Muller:
Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching Memories. 3
Design of Arithmetic VLSI Circuits
- Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez:
Arithmetic Data Path Optimization Using Borrow-Save Representation. 4-9 - Omid Kavehei
, Mostafa Rahimi Azghadi, Keivan Navi, Amir-Pasha Mirbaha:
Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design. 10-15
Architecture & SoC Design
- Zhonglei Wang, Thomas Wild, Stefan Rüping, Bernhard Lippmann:
Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design. 16-21 - Deniz Dal
Determining the Optimal Number of Islands in Power Islands Synthesis. 22-27
Emerging Technologies
- Asbjørn Djupdal, Pauline C. Haddow:
Defect Tolerance Inspired by Artificial Evolution. 28-33 - Ismo Hänninen, Jarmo Takala
Reliability of n-Bit Nanotechnology Adder. 34-39 - Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer:
Spintronic Device Based Non-volatile Low Standby Power SRAM. 40-45
Heterogeneous System Design
- Fahd Ben Abdeljelil, Benjamin Nicolle, William Tatinian, Lorenzo Carpineto, Jean Oudinot, Gilles Jacquemod:
Application of Bottom-Up Methodology to RTW VCO. 46-50 - Olivier Leman, Laurent Latorre, Frédérick Mailly
A Closed-Loop Architecture with Digital Output for Convective Accelerometers. 51-56 - Boris Alandry, Norbert Dumas, Laurent Latorre, Frédérick Mailly
A CMOS Multi-sensor System for 3D Orientation Determination. 57-62
Low Power Design I
- Nainesh Agarwal, Nikitas J. Dimopoulos:
FSMD Partitioning for Low Power Using ILP. 63-68 - Shingo Watanabe, Toshinori Sato
Uncriticality-Directed Low-Power Instruction Scheduling. 69-74 - Karthik Sabhanatarajan, Ann Gordon-Ross, Mark Oden, Mukund Navada, Alan D. George
Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices. 75-80 - Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
BTB Access Filtering: A Low Energy and High Performance Design. 81-86
Multiprocessor SoC
- Ralf Laue, H. Gregor Molter
A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications. 87-92 - Issam Maalej, Guy Gogniat
System Level Design Space Exploration for Multiprocessor System on Chip. 93-98 - Theocharis Theocharides
A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures. 99-104 - Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert:
MPI-Based Adaptive Task Migration Support on the HS-Scale System. 105-110
Low Power Design II
- Bahar Jalali Farahani, Anand Meruva:
Low Power High Performance Digitally Assisted Pipelined ADC. 111-116 - Rong Ji, Liang Chen, Gang Luo, Xianjun Zeng, Junfeng Zhang, Yingjie Feng:
A Novel Low-Power Clock Skew Compensation Circuit. 117-121 - Yngvar Berg, Omid Mirmotahari
High Speed Ultra Low Voltage CMOS inverter. 122-127 - Lingamneni Avinash, Kirthi Krishna Muntimadugu, M. B. Srinivas:
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection. 128-133
System Level Testing
- Jingbo Shao, Guangsheng Ma, Zhi Yang, Ruixue Zhang:
Process Algebra Based SoC Test Scheduling for Test Time Minimization. 134-138 - Julien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre:
Improving the Test of NoC-Based SoCs with Help of Compression Schemes. 139-144 - Michael Higgins, Ciaran MacNamee
A Novel System on Chip (SoC) Test Solution. 145-150 - Nestor Hernandez, Víctor H. Champac:
Testing Skew and Logic Faults in SoC Interconnects. 151-156
High Performance Circuits
- Qingsheng Hu, Hua-An Zhao, Chen Liu:
A Programmable Frequency Divider in 0.18µm CMOS Library. 157-161 - Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William G. Dunford, Patrick R. Palmer
Energy Recovery from High-Frequency Clocks Using DC-DC Converters. 162-167
Mixed Signal Design
- Xiao Pu, Axel Thomsen, Jacob A. Abraham:
Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL. 168-172 - Ahmed El Oualkadi
Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications. 173-178
Nanoscale Circuits
- David Bol, Renaud Ambroise, Denis Flandre
Impact of Technology Scaling on Digital Subthreshold Circuits. 179-184 - Behzad Ebrahimi
Low Standby Power and Robust FinFET Based SRAM Design. 185-190 - Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz:
CMOS Control Enabled Single-Type FET NASIC. 191-196
Telecom & Multimedia Architecture Design and Modeling
- V. K. Prasad Arava, Manhwee Jo, HyoukJoong Lee, Kiyoung Choi:
A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines. 197-202 - Grzegorz Pastuszak
Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection. 203-208 - Ali Ahmadinia, Balal Ahmad, Tughrul Arslan:
Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications. 209-214
Physical Design
- Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian
Performance Improvement of Physical Retiming with Shortcut Insertion. 215-220 - Yibo Wang, Yici Cai, Xianlong Hong:
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. 221-226 - Gustavo Wilke, Ricardo Reis:
A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction. 227-232 - Arash Mehdizadeh, Morteza Saheb Zamani
An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. 233-238
Test & Verification
- Selina Sha, Bruce Swanson:
A Real Case of Significant Scan Test Cost Reduction. 239-244 - Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan:
A Network Based Functional Verification Method of IEEE 1394a PHY Core. 245-250 - Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan:
Cohesive Coverage Management for Simulation and Formal Property Verification. 251-256 - Ilia Polian, Sudhakar M. Reddy, Bernd Becker
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. 257-262
Models for low Power Design
- Ajit Gupte, Mohit Sharma, Gaurav Varshney, Lakshmikantha Holla, Parvinder Rana, H. Udayakumar:
Memory Power Modeling - A Novel Approach. 263-268 - Sambhu Nath Pradhan
Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. 269-274 - Ali Ahmadinia, Balal Ahmad, Tughrul Arslan:
Efficient High-Level Power Estimation for Multi-standard Wireless Systems. 275-280 - Adnan Kabbani:
Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits. 281-285
Dynamic Reconfiguration Management Techniques
- Massimo Morandi, Marco Novati, Marco D. Santambrogio
Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture. 286-291 - Krzysztof Kepa
SeReCon: A Secure Dynamic Partial Reconfiguration Controller. 292-297 - Maik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke:
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs. 298-303 - Katarina Paulsson, Ulrich Viereck, Michael Hübner, Jürgen Becker:
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. 304-309
Hot Topic : Variability-Insensitive Design Techniques
- Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert:
Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects. 310-315 - Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. 316-321 - N. Pete Sedcole, Justin S. J. Wong
Characterisation of FPGA Clock Variability. 322-328 - Venkataraman Mahalingam, Nagarajan Ranganathan:
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. 329-334
Network On Chip
- Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, Sao-Jie Chen
Flow Maximization for NoC Routing Algorithms. 335-340 - Everton Carara, Fernando Gehm Moraes
Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip. 341-346 - Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. 347-352
VLSI Circuits
- V. Suresh Babu
Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance Amplifier. 353-356 - Roberto Perez-Andrade, René Cumplido, Fernando Martin del Campo, Claudia Feregrino Uribe:
A Versatile Linear Insertion Sorter Based on a FIFO Scheme. 357-362
Hot Topic : Temperature-aware Design
- Hamid Noori
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. 363-368 - Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. 369-374 - Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory. 375-380
Reconfigurable-based Circuits & Methods
- Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin:
Standard Cell Like Via-Configurable Logic Block for Structured ASICs. 381-386 - Andreas Hofmann, Klaus Waldschmidt:
SDVM-R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-Chip. 387-392 - Mohamed B. Abdelhalim
Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme. 393-398 - Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani
FPGA-Based Circuit Model Emulation of Quantum Algorithms. 399-404
System Level Design & Tools
- David Andreu
Petri Net Based Rapid Prototyping of Digital Complex System. 405-410 - Robert Wille
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. 411-416 - Fabrizio Ferrandi
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis. 417-422 - Hariharan Sankaran, Srinivas Katkoori
Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis. 423-428
Posters 1
- P. Balasubramanian, David A. Edwards:
Efficient Realization of Strongly Indicating Function Blocks. 429-432 - Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol:
Virtual Point-to-Point Links in Packet-Switched NoCs. 433-436 - Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled:
Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip. 437-440 - Sunil Shukla, Neil W. Bergmann
A Web Server Based Edge Detector Implementation in FPGA. 441-446 - Maziar Goudarzi
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. 447-450 - Serge Burckel, Emeric Gioan:
In Situ Design of Register Operations. 451-454 - Hongbin Sun, Nanning Zheng, Chenyang Ge, Dong Wang, Pengju Ren:
An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design. 455-458 - Rupsa Chakraborty, Dipanwita Roy Chowdhury:
Raising the Level of Abstraction for the Timing Verification of System-on-Chips. 459-462 - Hugo Lebreton, Pascal Vivet
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. 463-466 - Minoo Mirsaeedi, Morteza Saheb Zamani
Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. 467-470 - Yasaman Sanaee, Mehdi Saeedi
Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. 471-474
Posters 2
- Guilherme Montez Guindani, Cezar Reinbrecht, Thiago Raupp da Rosa, Ney Calazans
NoC Power Estimation at the RTL Abstraction Level. 475-478 - Ahmed Jedidi
Design of Fractal Image Compression on SOC. 479-482 - Jin-Hua Hong, Wen-Jie Li:
A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier. 483-486 - Fabien Soulier, Jean-Baptiste Lerat, Lionel Gouyet, Serge Bernard
A Neural Stimulator Output Stage for Dodecapolar Electrodes. 487-490 - Leandro Soares Indrusiak
Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. 491-494 - Yosi Ben-Asher, Eddie Shochat:
Finding the Best Compromise in Compiling Compound Loops to Verilog. 495-498 - Xun Zhang, Hassan Rabah
An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip. 499-502 - Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang:
An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. 503-506 - Mehrdad Najibi, Hossein Pedram:
Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading. 507-510 - Daisaku Seto, Minoru Watanabe:
A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory. 511-514
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-28 20:36 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: