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ISQED 2002: San Jose, California, USA
- 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002. IEEE Computer Society 2002, ISBN 0-7695-1561-4
Tutorials: Test Methodologies for Quality Designs
- Geir Eide:
Design-for-Test Techniques for SoC Designs (Tutorial Abstract). 7 - Sreejit Chakravarty:
Supplemental Test Methods (Tutorial Abstract). 7
Tutorials: Design for Reliability in UDSM: Issues and Solutions
- Charvaka Duvvury:
Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract). 8 - J. Joseph Clement:
Electromigration Reliability Issues in High-Performance Circuit Design (Tutorial Abstract). 8 - John S. Suehle:
Ultra-thin Gate Oxide Reliability and Implications for Design (Tutorial Abstract). 9 - Shain Aur:
Hot Carrier Reliability and Design Considerations (Tutorial Abstract). 9
Interconnect and Device Modeling for Quality Design
- Norman Chang:
Power/Ground Integrity Issues for Sub-130nm IC Designs (Tutorial Abstract). 10 - Ersed Akcasu:
A General and Comparative Study of RC(0), RC, RCL and RCLK Modeling of Interconnects and Their Impact on the Design of Multi-Giga Hertz Processors (Tutorial Abstract). 10 - Daniel Foty:
MOS Modeling, Design Quality, and Modern Analog Design (Tutorial Abstract). 11 - Li-Fu Chang:
RLCK Extraction and Simulation in High-Speed SoC Designs (Tutorial Abstract). 11
Tutorials: Design Flows and Methodologies
- Sumit Ghosh:
nVHDL: A Hardware Design Language for Modeling Discrete and Analog Design and Simulation of Mixed-Signal Electronic Systems (Tutorial Abstract). 12 - Henry Chang:
Platform-Based Design: A Tutorial (Tutorial Abstract). 12 - Andrew Marshall:
Quality Aspects of SOI Circuit Design (Tutorial Abstract). 13 - Olivier Coudert:
Optimization in an Integrated Physical Design Flow (Tutorial Abstract). 13-14 - Pallab K. Chatterjee, Richard Goering:
Evening Panel Discussion: Are the Interoperability Standards for EDA Too Little/Too Late for Real SoC Designs? 15
Plenary Session I
- John Chilton:
IP REUSE QUALITY: "Intellectual Property" or "Intense Pain"? 21-22 - Y. Lepejian:
Why Integrated Yield Management is a Necessity. 23-24 - Jim Kupec:
Design Success: Foundry Perspective. 25-26 - Y. C. Pati:
What You Don't Know CAN Hurt You: Designing for Survival in a Sub-wavelength Environment. 27-
Interconnect Extraction and Modeling
- Rafael Reif, Andy Fan, Kuan-Neng Chen
, Shamik Das:
Fabrication Technologies for Three-Dimensional Integrated Circuits (invited). 33-37 - Vikram Jandhyala, Yong Wang
Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. 38-42 - Kaustav Banerjee, Amit Mehrotra:
Inductance Aware Interconnect Scaling. 43-47 - Gaofeng Wang
Accurate Model of Metal-Insulator-Semiconductor Interconnects. 48-52 - Himanshu Kaul, Dennis Sylvester:
Transition Aware Global Signaling (TAGS). 53-59
Quality and Interoperability of EDA Tools
- Daniel Moritz:
Using the Open Library Architecture (OLA) Open Source API in Heterogeneous Design Flows (invited). 63-68 - Terry Blanchard, Rick Ferreri, Jim Wilmore:
The OpenAccess Coalition - The Drive to an Open Industry Standard Information Model, API, and Reference Implementation for IC Design Data (invited). 69-74 - Ralf Seepold
A Qualification Platform for Design Reuse. 75-80 - Giora Ben-Yaacov, Pramod Suratkar, Marsha Holliday, Karen Bartleson:
Advancing Quality of EDA Software (invited). 81-86 - Aleksander Slusarczyk, Lech Józwiak:
Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. 87-92
Design for Test
- Robert C. Aitken:
Test Generation and Fault Modeling for Stress Testing (invited). 95-99 - Y. Tsiatouhas
Extending the Viability of IDDQ Testing in the Deep Submicron Era. 100-105 - Sandeep Koranne:
Design of Reconfigurable Access Wrappers for Embedded Core Based SoC Test. 106-111 - Daniela De Venuto
Testing of Analogue Circuits via (Standard) Digital Gates. 112-119 - Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda
Automatic Test Program Generation from RT-Level Microprocessor Descriptions. 120-125
Design for Process Variations
- Enrico Malavasi, Stefano Zanella, Min Cao, Julian Uschersohn, Mike Misheloff, Carlo Guardiani:
Impact Analysis of Process Variability on Clock Skew. 129-132 - Michael Kocher, Gerhard Rappitsch:
Statistical Methods for the Determination of Process Corners. 133-127 - Daegyu Lee, Jincheol Yoo, Kyusun Choi:
Design Method and Automation of Comparator Generation for Flash A/D Converter. 138-142 - Chul-Hong Park, Soo-Han Choi, Sang-Uhk Rhie, Dong-Hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong:
A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and Beyond. 143-147 - Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun:
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. 148-153
Power, Signal and EMI Analysis and Optimization
- Ting-Yuan Wang, Charlie Chung-Ping Chen:
Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm. 157-162 - Geng Bai, Ibrahim N. Hajj:
Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network. 163-168 - Kenji Shimazaki, Shouzou Hirano, Hiroyuki Tsujikawa:
An EMI-Noise Analysis on LSI Design with Impedance Estimation. 169-174 - Abby A. Ilumoka:
Chip Level Signal Integrity Analysis & Crosstalk Prediction Using Artificial Neural Nets. 175-180 - Wendemagegnehu T. Beyene, Chuck Yuan:
On the Use of Windows for Accurate Analysis of Package Interconnects. 181-186
Methods and Metrics for Design Quality
- Daniel N. Maynard:
Productivity Optimization Techniques for the Proactive Semiconductor Manufacturer (invited). 189 - Andrew B. Kahng, Gary Smith:
A New Design Cost Model for the 2001 ITRS (invited). 190-193 - Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan:
Optimal Sequencing Energy Allocation for CMOS Integrated Systems. 194-199 - J. M. Gilbert, Ian M. Bell, D. R. Johnson:
Design, Manufacture and Test - Quality Test Estimation. 200-205 - Andrew B. Kahng, Stefanus Mantik:
Measurement of Inherent Noise in EDA Tools. 206-212 - Ron Wilson, Siva G. Narendra, Vivek De:
Evening Panel Discussion: Process Variation: Is It Too Much to Handle? 213-
Plenary Session II
- Atiq Raza:
The Role of ICs in the Creation of a Connected World and the Importance of Product Quality. 219-220 - Bob Brodersen:
Wireless Systems-on-a-Chip Design. 221-222 - Chan Wu:
Microwave III-V Semiconductors for Telecommunications and Prospective of the III-V Industry. 223-224 - Ulf Schlichtmann:
Tomorrows High-Quality SoCs Require High-Quality Embedded Memories Today. 225-
Poster Session
- Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of Selectively Clocked Skewed Logic Circuits. 229-234 - Bok-Gue Park, Koon-Shik Cho, Jun Dong Cho
Low Power VLSI Architecture of Viterbi Scorer for HMM-Based Isolated Word Recognition. 235-239 - Dinesh Pamunuwa
On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. 240-245 - Syed M. Alam, Donald E. Troxel, Carl V. Thompson:
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits. 246-251 - Zhuo Gao, Ji Luo, Hu Huang, Wei Zhang, Joseph B. Bernstein
Reliable Laser Programmable Gate Array Technology. 252-256 - Pierre Bricaud:
VC Rating and Quality Metrics: Why Bother? 257-260 - Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. 261-266 - Sule Ozev, Alex Orailoglu:
An Integrated Tool for Analog Test Generation and Fault Simulation. 267-272 - Gert Jervan
A Hybrid BIST Architecture and Its Optimization for SoC Testing. 273-279 - Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham:
Native Mode Functional Self-Test Generation for Systems-on-Chip. 280-285 - Mandeep Singh, Israel Koren:
Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs). 286-291 - Parag K. Lala, B. Kiran Kumar:
Human Immune System Inspired Architecture for Self-Healing Digital Systems. 292-297 - Grégory Servel, Denis Deschacht, Françoise Saliou, Jean-Luc Mattei, Fabrice Huret:
Impact of Low-K on Crosstalk. 298-303 - Amjad Hajjar, Tom Chen:
Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. 304-309 - Sumit Ghosh:
In Search of the Origin of VHDL's Delta Delays. 310-315 - Andrey V. Mezhiba, Eby G. Friedman:
Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits. 316-321 - Jin-Kyu Park, Keun-Ho Lee, Chang-Sub Lee, Gi-Young Yang, Young-Kwan Park, Jeong-Taek Kong:
Characterizing the Current Degradation of Abnormally Structured MOS Transistors Using a 3D Poisson Solver. 322-325 - Tae-young Oh, Zhiping Yu, Robert W. Dutton:
AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections. 326-330 - Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo:
ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process. 331-336 - Naoyuki Shigyo, Hirobumi Kawashima, Seiji Yasuda:
Design of ESD Protection Device Using Statistical Methods. 337-340 - Mehmet Sahinoglu, Scott Glover:
Economic Analysis of a Stopping-rule in Branch Coverage Testing. 341-346
Design Issues for Power and Noise Management
- David Scott, Shaoping Tang, Song Zhao, Mahalingam Nandakumar:
Device Physics Impact on Low Leakage, High Speed DSP Design Techniques (invited). 349-354 - Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Power Supply Noise Suppression via Clock Skew Scheduling. 355-360 - Atul Maheshwari, Wayne P. Burleson, Russell Tessier:
Trading off Reliability and Power-Consumption in Ultra-low Power Systems. 361-366 - Peter A. Beerel
Asynchronous Circuits: An Increasingly Practical Design Solution (invited). 367-372 - Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama:
Trends in Low Power Digital System-on-Chip Designs (invited). 373-378
Verification in Achieving Design Quality
- Shaz Qadeer, Serdar Tasiran:
Promising Directions in Hardware Design Verification (invited). 381-387 - Sébastien Pillement, Daniel Chillet
Behavioral IP Specification and Integration Framework for High-Level Design Reuse. 388-393 - Sherief Reda, Rolf Drechsler
On the Relation between SAT and BDDs for Equivalence Checking. 394-399 - José R. Sendra, Javier del Pino
Integrated Inductors Modeling and Tools for Automatic Selection and Layout Generation. 400-404 - Nguyen Quang Trung, Artur Kokoszka, Krystyna Siekierska, Adam Pawlak, Dariusz Obrebski, Norbert Lugowski:
Organization of a Microprocessor Design Process Using Internet-Based Interoperable Workflows. 405-410
Signal Integrity
- Murat R. Becer, Rajendran Panda, David T. Blaauw, Ibrahim N. Hajj:
Pre-route Noise Estimation in Deep Submicron Integrated Circuits. 413-418 - Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi:
Time-Domain Simulation of Variational Interconnect Models. 419-424 - Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Chanhee Oh:
Noise Injection and Propagation in High Performance Designs. 425-430 - Lauren Hui Chen, Malgorzata Marek-Sadowska:
Efficient Closed-Form Crosstalk Delay Metrics. 431-436 - Alexey Glebov, Sergey Gavrilov
False-Noise Analysis Using Resolution Method. 437-442
Low Power Design Techniques
- Takayasu Sakurai:
Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited). 445-450 - Radu Marculescu
Does Q=MC2? (On the Relationship between Quality in Electronic Design and the Model of Colloidal Computing, invited). 451-457 - Geun Rae Cho, Tom Chen:
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. 458-463 - Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh:
Structural Decomposition with Functional Considerations for Low Power. 464-469 - Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram:
ALBORZ: Address Level Bus Power Optimization. 470-475
Advanced Device Technology Issues in Circuit Design
- David A. Sunderland, Gary L. Duncan, Brad J. Rasmussen, Harry E. Nichols, Daniel T. Kain, Lawrence C. Lee, Brian A. Clebowicz, Richard W. Hollis IV, Larry Wissel, Tad Wilder:
Megagate ASICs for the Thuraya Satellite Digital Signal Processor (invited). 479-486 - Pin Su, Samel K. H. Fung, Weidong Liu, Chenming Hu:
Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD. 487-491 - Meikei Leong, H.-S. Philip Wong, Edward J. Nowak, Jakub Kedzierski, Erin C. Jones:
High Performance Double-Gate Device Technology Challenges and Opportunities (invited). 492-495 - Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, Philippe Renaud, C. Hibert, Philippe Flückiger, G. A. Racine:
Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture. 496-501 - Christoph Wasshuber:
Single-Electronics - How It Works. How It's Used. How It's Simulated (invited). 502-507
Design, Planning and Closure
- Olivier Coudert:
Timing and Design Closure in Physical Design Flows (invited). 511-516 - Chee How Lim, W. Robert Daasch, George Cai:
A Thermal-Aware Superscalar Microprocessor (invited). 517-522 - Nicholas Chia-Yuan Chang, Yao-Wen Chang
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. 523-528 - Wei-Jin Dai, Michel Courtoy:
Hierarchical Front-End Physical Design Solution Drives Modified Hand-Off (invited). 529-533 - Charlie Chung-Ping Chen, Ed Cheng:
Future SoC Design Challenges and Solutions (invited). 534-538
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