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iNIS 2016: Gwalior, India
- IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016. IEEE 2016, ISBN 978-1-5090-6170-9
- Md. Fahad, Zhou Zhao, Ashok Srivastava, Lu Peng:
Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design. 1-5 - Yaser Mohammadi Banadaki
, Ashok Srivastava:
Width-Dependent Characteristics of Graphene Nanoribbon Field Effect Transistor for High Frequency Applications. 6-10 - Ramesh Kumar, Rohit Dhiman, Rajeevan Chandel
Performance Analysis of Top-Contact MLGNR Based Interconnects. 11-16 - Prabha Sundaravadivel, Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka, Himanshu Thapliyal
Exploring Human Body Communications for IoT Enabled Ambulatory Health Monitoring Systems. 17-22 - Shalom Greene, Himanshu Thapliyal
IoT-Based Fall Detection for Smart Home Environments. 23-28 - Sushmita Dandeliya
Ni-CNT as Isopropanol Sensor: Ab-Initio Analysis. 29-33 - Kamilya Smagulova
CMOS-Memristor Hybrid Integrated Pixel Sensors. 34-37 - Yeduri Sreenivasa Reddy, K. K. Pattanaik
A Reply Cache Mechanism to Reduce Query Latency of WSN in IoT Sensory Environment. 38-42 - Saurabh B. Kaurati, Nithin Y. B. Kumar
Design and Implementation of Tunable Bandpass Filter for Biomedical Applications. 43-46 - Gaurav Sharma
A 4X1 High-Definition Transcranial Direct Current Stimulation Device for Targeting Cerebral Micro Vessels and Functionality Using NIRS. 47-51 - Pranshu Kalra, Shaista Hussain, Nitin Chaturvedi:
An Investigation of Power-Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems. 52-55 - Sudeendra Kumar K, Naini Satheesh, Abhishek Mahapatra, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
Securing IEEE 1687 Standard On-chip Instrumentation Access Using PUF. 56-61 - Azhar Syed, R. Mary Lourde
Hardware Security Threats to DSP Applications in an IoT Network. 62-66 - Disha Yadav, Arvind Rajawat
Area and Throughput Analysis of Different AES Architectures for FPGA Implementations. 67-71 - Santanu K. Mishra
Power Converter Systems for Consumer Electronics Devices. 72-75 - Shital Joshi, Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka:
Graphene Nanoribbon Field Effect Transistor Based Ultra-Low Energy SRAM Design. 76-79 - Deepak Kachave, Anirban Sengupta:
Protecting Ownership of Reusable IP Core Generated during High Level Synthesis. 80-82 - C. Anju, Nisha Kuruvilla, T. E. Ayoob Khan
Performance Analysis of Wavy FinFET and Optimization for Leakage Reduction. 83-88 - Vivek Kumar, Vikas Mahor, Manisha Pattanaik:
Novel Ultra Low Leakage FinFET Based SRAM Cell. 89-92 - Vikash Sehwag, Saurav Maji, Mrigank Sharad:
Variation Aware Performance Analysis of TFETs for Low-Voltage Computing. 93-97 - Ojashri Sharma, Aakash Saini, Sandeep Saini
A Quadro Coding Technique to Reduce Self Transitions in VLSI Interconnects. 98-101 - Pawan Sehgal, Akhilesh C. Mishra, Rangarajan Ramanujam, Sujay Deb
An Efficient Approach Targeting Broken Topological Clock Path for Master - Generated Clock Pair. 102-107 - Ayas Kanta Swain, Anil Kumar Rajput, Kamalakanta Mahapatra:
Parametric Performance Analysis of Synchronous and Asynchronous Heterogeneous Network on Chip. 108-112 - Boddepalli Santhi Bhushan, Anurag Srivastava, Jyoti Bhadouria, Rinkoo Bhatia
Aromaticity Influence on Electron Transport of Molecular Single Electron Transistor: DFT Investigation. 113-117 - Chaitanya Maradana, Jawar Singh
Proposal of Heterogate Technique for Performance Enhancement of DM-TFET. 118-123 - Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav
Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter. 124-128 - Mayukh Sarkar
Post CMOS Computing Beyond Si: DNA Computer as Future Alternative. 129-133 - Swapan Shakhari
A Provably Good Method to Generate Good DNA Sequences. 134-138 - Abhishek Shrivastava, Ajay Pratap Gangwar, Rahul Kumar, Rohit Dhiman:
A 60 dB Bulk-Driven Rail-to-Rail Input/Output OTA. 139-143 - Antaryami Panigrahi
A 0.5V Voltage-Combiner Based Pseudo Differential OTA Design in CMOS Using Weakly Inverted Transistors. 144-148 - Chitrakant Sahu
Mixed-Mode Simulation of Common Emitter Amplifier Design Using Bipolar Charge Plasma Transistor. 149-154 - Samya Muhuri, Susanta Chakraborty, S. K. Setua:
An Edge Contribution-Based Approach to Identify Influential Nodes from Online Social Networks. 155-160 - Anand Kumar Gupta, Neetu Sardana:
Naïve Bayes Approach for Predicting Missing Links in Ego Networks. 161-165 - Raj Mani Shukla, Prasanna Kansakar, Arslan Munir
A Neural Network-Based Appliance Scheduling Methodology for Smart Homes and Buildings with Multiple Power Sources. 166-171 - Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos:
Novel FinFET Based Physical Unclonable Functions for Efficient Security Integration in the IoT. 172-177 - Naini Satheesh, Abhishek Mahapatra, Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
A Modified RO-PUF with Improved Security Metrics on FPGA. 178-181 - Vikash Sehwag, Tanujay Saha:
TV-PUF: A Fast Lightweight Analog Physical Unclonable Function. 182-186 - Sauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra, Ayas Kanta Swain:
A Novel Aging Tolerant RO-PUF for Low Power Application. 187-192 - Zoltan Lehoczky, Richárd Tóth, Mark Bartha, Andras Retzler, Benedek Farkas, Krisztian Somogyi:
Turning Software into Hardware - Hastlayer. 193 - Meena Panchore, Jawar Singh
Compact Behavioral Modeling and Time Dependent Performance Degradation Analysis of Junction and Doping Free Transistors. 194-199 - Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Jawar Singh
Secure Multi-key Generation Using Ring Oscillator Based Physical Unclonable Function. 200-205 - Prateek Singh, Deepali Singh, Ashish Sharma:
Classification of Non-functional Requirements from SRS Documents Using Thematic Roles. 206-207 - Raj Mani Shukla, Arslan Munir
A Computation Offloading Scheme Leveraging Parameter Tuning for Real-Time IoT Devices. 208-209 - Hemant Kumar
Optical Characteristics of Solution Processed MoO2/ZnO Quantum Dots Based Thin Film Transitor. 210-213 - Yogesh Kumar, Hemant Kumar
Electrical and Optical Characteristics of Pd/ZnO Quantum Dots Based Schottky Photodiode on n-Si. 214-217 - A. G. Rao, A. K. D. Dwivedi:
Design of ESOP-RPLA Array Using DRG2 and DRG4 Gates Based on Reversible Logic Technology. 218-223 - Kush Khanna, Bijaya Ketan Panigrahi, Anupam Joshi
Bid Modification Attack in Smart Grid for Monetary Benefits. 224-229 - Pratima Chatterjee, Mayukh Sarkar
Computing in Ribosomes: Implementing Sequential Circuits Using mRNA-Ribosome System. 230-235 - Muhammad Khalid
Memristor Crossbar-Based Pattern Recognition Circuit Using Perceptron Learning Rule. 236-239 - Mayukh Sarkar
Mathematics Using DNA: Performing GCD and LCM on a DNA Computer. 240-243 - Govinda Sannena, Bishnu Prasad Das:
Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application. 244-249 - Pritam Bhattacharjee
LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder. 250-254 - Saket Srivastava
Energy Detection Based Dynamic Spectrum Sensing for 2.4GHz ISM Band. 255-260 - Rituraj Singh Rathore
Impact of Work Function Fluctuations on Threshold Voltage Variability in a Nanoscale FinFETs. 261-263 - Nandakishor Yadav
Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET. 264-267 - Akanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor, Manisha Pattanaik:
Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell. 268-273 - Mukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor, Manisha Pattanaik:
FinFET-Based Low Power Address Decoder under Process Variation. 274-277 - Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas:
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. 278-283 - Binsu J. Kailath
QSCsim - Charge Based Switched Capacitor Simulator. 284
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last updated on 2024-12-29 20:18 CET by the dblp team
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