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ICCD 2011: Amherst, MA, USA
- IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1953-0
- Georgi Gaydadjiev
, Sofiène Tahar, Greg Byrd
Welcome to ICCD 2011!
Keynote Sessions
- Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Srinivas Devadas:
Memory coherence in the age of multicores. 1-8 - David R. Kaeli, David Akodes:
The convergence of HPC and embedded systems in our heterogeneous computing future. 9-11
Session 1
Networks on Chip (Systems Track)
- Jean-Michel Chabloz, Ahmed Hemani:
A GALS Network-on-Chip based on rationally-related frequencies. 12-18 - Ankit More, Baris Taskin:
EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs. 19-24 - Minjeong Shin, John Kim
Leveraging torus topology with deadlock recovery for cost-efficient on-chip network. 25-30 - Nicola Concer, Andrea Vesco
A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-Chip. 31-38
Efficient Energy Architectures (Architecture Track)
- Kai Ma, Xiaorui Wang, Yefu Wang:
DPPC: Dynamic power partitioning and capping in chip multiprocessors. 39-44 - Changshu Zhang, Arun Ravindran, Kushal Datta, Arindam Mukherjee, Bharat Joshi:
A machine learning approach to modeling power and performance of chip multiprocessors. 45-50 - Fahrettin Koc, Osman Seckin Simsek, Oguz Ergin
Using content-aware bitcells to reduce static energy dissipation. 51-56 - Jianmin Chen, Bin Li, Ying Zhang, Lu Peng, Jih-Kwon Peir:
Tree structured analysis on GPU power study. 57-64
Recent Advances in EDA (EDA Track)
- Jin-Tai Yan, Zhi-Wei Chen:
Pre-assignment RDL routing via extraction of maximal net sequence. 65-70 - Tong Xiao, Harshinder Bagga, George J. Chen, Richard Cheung, Raghu Pattipati:
Path aware event scheduler in HoldAdvisor for fixing min timing violations. 71-77 - Minoru Iizuka, Naohiro Hamada, Hiroshi Saito, Ryoichi Yamaguchi, Minoru Yoshinaga:
A tool set for the design of asynchronous circuits with bundled-data implementation. 78-83 - Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo
Applying verification intention for design customization via property mining under constrained testbenches. 84-89
Session 2
Test and Verification
- Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. 90-95 - Yu Zhang, Vishwani D. Agrawal:
Reduced complexity test generation algorithms for transition fault diagnosis. 96-101 - Yongjian Li, Naiju Zeng, William N. N. Hung, Xiaoyu Song:
Enhanced symbolic simulation of a round-robin arbiter. 102-107 - Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke:
Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation. 108-112
Microarchitectural Techniques (Architecture Track)
- Daniel A. Jiménez:
An optimized scaled neural branch predictor. 113-118 - Zichao Xie, Dong Tong, Mingkai Huang, Xiaoyin Wang, Qinqing Shi, Xu Cheng:
TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers. 119-126 - Komal Jothi, Mageda Sharafeddine
Simultaneous continual flow pipeline architecture. 127-134 - Yuejian Xie, Gabriel H. Loh:
Thread-aware dynamic shared cache compression in multi-core processors. 135-141
Memristor and Signal Processing (Logic and Circuits Track)
- Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman:
Memristor-based IMPLY logic design procedure. 142-147 - Pilin Junsangsri, Fabrizio Lombardi:
A memristor-based memory cell using ambipolar operation. 148-153 - Peng Li, David J. Lilja:
Using stochastic computing to implement digital image processing algorithms. 154-161 - Vladimir Risojevic, Aleksej Avramovic, Zdenka Babic, Patricio Bulic:
A simple pipelined squaring circuit for DSP. 162-167
Session 3
Energy and Thermal-Aware Design (Systems Track)
- Brad K. Donohoo, Chris Ohlsen, Sudeep Pasricha:
AURA: An application and user interaction aware middleware framework for energy optimization in mobile devices. 168-174 - Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie:
Energy-efficient multi-level cell phase-change memory system with data encoding. 175-182 - Yen-Kuan Wu, Shervin Sharifi, Tajana Simunic Rosing:
Distributed thermal management for embedded heterogeneous MPSoCs with dedicated hardware accelerators. 183-189 - Mohammad A. Haque, Hakan Aydin, Dakai Zhu:
Energy-aware Standby-Sparing Technique for periodic real-time applications. 190-197 - Arslan Munir
A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems. 198-205
Reversible Logic and Special Arithmetic Blocks (Logic and Circuits Track)
- Sayeeda Sultana, Katarzyna Radecka, Yu Pang:
A study on relating redundancy removal in classical circuits to reversible mapping. 206-211 - Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka:
Positive Davio-based synthesis algorithm for reversible logic. 212-218 - Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo:
Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA. 219-225 - Osama Daifallah Al-Khaleel, Zakaria Al-Qudah, Mohammad Al-Khaleel
Fast and compact binary-to-BCD conversion circuits for decimal multiplication. 226-231
Session 4
Best Papers
- Anh Thien Tran, Bevan M. Baas:
RoShaQ: High-performance on-chip router with shared queues. 232-238 - Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser:
Hybrid system level power consumption estimation for FPGA-based MPSoC. 239-246
Session 5
New Techniques for System-Level Simulation and Optimization (EDA Track)
- Deepak Gangadharan
Video quality-driven buffer dimensioning in MPSoC platforms via prioritized frame drops. 247-252 - Tyler S. Harris, Zhuo Ruan, David A. Penry:
Techniques for LI-BDN synthesis for hybrid microarchitectural simulation. 253-260 - Yu Liu, Kaijie Wu:
Runtime adaptable concurrent error detection for linear digital systems. 261-266
Topology and Physical Design (Logic and Circuits Track)
- Wei Shi, Weixia Xu, Hongguang Ren, Qiang Dou, Zhiying Wang, Li Shen, Cong Liu:
A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer. 267-272 - Ying Teng, Jianchao Lu, Baris Taskin:
ROA-brick topology for rotary resonant clocks. 273-278 - Vinícius Dal Bem, Paulo F. Butzen
Impact and optimization of lithography-aware regular layout in digital circuit design. 279-284
Session 6
Special Session on Hardware Trust: Capture the Chip
- Jeyavijayan Rajendran, Vinayaka Jyothi, Ramesh Karri
Blue team red team approach to hardware trust assessment. 285-288 - Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno:
Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. 289-292 - Trey Reece
Hardware Trojans: The defense and attack of integrated circuits. 293-296 - Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Tatini Mal-Sarkar, Swarup Bhunia
Sequential hardware Trojan: Side-channel aware design and placement. 297-300 - Georg T. Becker, Ashwin Lakshminarasimhan, Lang Lin, Sudheendra Srivathsa, Vikram B. Suresh, Wayne P. Burleson:
Implementing hardware Trojans: Experiences from a hardware Trojan challenge. 301-304 - Yier Jin
Is single-scheme Trojan prevention sufficient? 305-308 - Xuehui Zhang, Nicholas Tuzzio, Mohammad Tehranipoor:
Red team: Design of intelligent hardware trojans with known defense schemes. 309-312
Session 7
Memories and Caches (Logic and Circuits Track)
- Kyohei Yamaguchi, Yuya Kora, Hideki Ando:
Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path. 313-319 - Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset. 320-325 - Farshad Moradi
Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. 326-331 - Shrikanth Ganapathy, Ramon Canal, Antonio González
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors. 332-338
Systems Potpourri (Systems Track)
- Domenic Forte
Adaptable architectures for distributed visual target tracking. 339-345 - Artem Durytskyy, Mohamed Zahran
Improving GPU Robustness by making use of faulty parts. 346-351 - Rawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio, Valeria Bertacco:
Functional correctness for CMP interconnects. 352-359 - Bharath Phanibhushana, Kunal P. Ganeshpure, Sandip Kundu:
Task model for on-chip communication infrastructure design for multicore systems. 360-365
Session 8
Memory and Cache Architectures (Systems Track)
- Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie:
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory. 366-372 - Mohammad Arjomand, Amin Jadidi, Ali Shafiee, Hamid Sarbazi-Azad:
A morphable phase change memory architecture considering frequent zero values. 373-380 - Hyung Gyu Lee, Seungcheol Baek
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems. 381-387 - Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, M. Frank Chang
The DIMM tree architecture: A high bandwidth and scalable memory system. 388-395
Reliable and Adaptive Architectures (Architecture Track)
- Marisha Rawlins, Ann Gordon-Ross:
CPACT - The conditional parameter adjustment cache tuner for dual-core architectures. 396-403 - Michael Gschwind, Valentina Salapura, Catherine Trammell, Sally A. McKee:
SoftBeam: Precise tracking of transient faults and vulnerability analysis at processor design time. 404-410 - Omer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas:
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores. 411-418 - Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. 419-426
Poster Session
- Yong Zou, Yi Xiang, Sudeep Pasricha:
Analysis of on-chip interconnection network interface reliability in multicore systems. 427-428 - Nan Li, Elena Dubrova:
AIG rewriting using 5-input cuts. 429-430 - Gulay Yalcin, Osman S. Unsal
FIMSIM: A fault injection infrastructure for microarchitectural simulators. 431-432 - Reyhaneh Jabbarvand Behrouz, Mehdi Modarressi, Hamid Sarbazi-Azad:
A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults. 433-434 - Sourindra Chaudhuri, Niraj K. Jha:
3D vs. 2D analysis of FinFET logic gates under process variations. 435-436 - Daniel Y. Deng, G. Edward Suh
Precise exception support for decoupled run-time monitoring architectures. 437-438 - Vikram G. Rao, Hamid Mahmoodi
Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology. 439-440 - Thierry Bonnoit
Towards a tool for implementing delay-free ECC in embedded memories. 441-442 - Da Cheng, Sandeep Gupta:
A novel software-based defect-tolerance approach for application-specific embedded systems. 443-444 - Fahimeh Jafari, Axel Jantsch
Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling. 445-446 - Vish Ganti, Hamid Mahmoodi
Comparative analysis of copper and CNT interconnects for H-tree clock distribution. 447-448 - Amr M. A. Hussien, Ahmed M. Eltawil
Energy aware task mapping algorithm for heterogeneous MPSoC based architectures. 449-450 - Pey-Chang Kent Lin, Alex Ivanov, Bradley Johnson, Sunil P. Khatri:
A novel cryptographic key exchange scheme using resistors. 451-452 - Kai Du, Peter J. Varman
Static window addition: A new paradigm for the design of variable latency adders. 455-456 - Domenic Forte
Energy-aware and quality-scalable data placement and retrieval for disks in video server environments. 457-458 - Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
Low power, high throughput network-on-chip fabric for 3D multicore processors. 453-454
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