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16th HPCA 2010: Bangalore, India
- Matthew T. Jacob, Chita R. Das, Pradip Bose:
16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 9-14 January 2010, Bangalore, India. IEEE Computer Society 2010, ISBN 978-1-4244-5659-8
Keynote Session I
- Tilak Agerwala:
Exascale computing: The challenges and opportunities in the next decade. 1
Best Paper Nominees
- Muhammad Umar Farooq, Lei Chen, Lizy Kurian John:
Value Based BTB Indexing for indirect jump prediction. 1-11 - Tong Li, Paul Brett, Rob C. Knauerhase
, David A. Koufaty, Dheeraj Reddy, Scott Hahn:
Operating system support for overlapping-ISA heterogeneous multi-core architectures. 1-12 - David Champagne, Ruby B. Lee:
Scalable architectural support for trusted software. 1-12 - Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter:
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. 1-12
Multicore Architectures
- Fang Liu, Xiaowei Jiang, Yan Solihin:
Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance. 1-12 - Brian Greskamp, Ulya R. Karpuzcu, Josep Torrellas:
LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores. 1-12 - Syed Ali Raza Jafri, Mithuna Thottethodi
LiteTM: Reducing transactional state overhead. 1-12 - Dimitris Kaseridis, Jeffrey Stuecheli, Jian Chen, Lizy Kurian John:
A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems. 1-11
Reliability and Energy Efficiency
- Ioannis Doudalis, Milos Prvulovic:
HARE: Hardware assisted reverse execution. 1-12 - Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Designing a processor from the ground up to allow voltage/reliability tradeoffs. 1-11 - Mingsong Bi, Igor Crk, Chris Gniady:
IADVS: On-demand performance for interactive applications. 1-10 - Guangyu Sun, Yongsoo Joo
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. 1-12
Panel
- Josep Torrellas, Bill Gropp, Vivek Sarkar, Jaime H. Moreno, Kunle Olukotun:
Extreme scale computing: Challenges and opportunities. 1
Keynote
- Arvind:
Is hardware innovation over? 1
Memory Systems
- Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño:
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing. 1-11 - Nikola Vujic, Marc González, Felipe Cabarcas, Alex Ramírez, Xavier Martorell, Eduard Ayguadé:
DMA++: on the fly data realignment for on-chip memories. 1-12 - Mingsong Bi, Ran Duan, Chris Gniady:
Delay-Hiding energy management mechanisms for DRAM. 1-10
Cache Architectures
- Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy:
UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all. 1-12 - Hyunjin Lee, Sangyeun Cho, Bruce R. Childers:
StimulusCache: Boosting performance of chip multiprocessors with excess cache. 1-12 - Javier Merino, Valentin Puente, José-Ángel Gregorio
ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture. 1-10 - Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian:
CHOP: Adaptive filter-based DRAM caching for CMP server platforms. 1-12
On-Chip Networks and IO
- Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian:
Towards scalable, energy-efficient, bus-based on-chip networks. 1-12 - Yi Xu, Bo Zhao, Youtao Zhang, Jun Yang:
Simple virtual channel allocation for high throughput and high frequency on-chip routers. 1-11 - Yaozu Dong, Xiaowei Yang, Xiaoyong Li, Jianhui Li, Kun Tian, Haibing Guan:
High performance network virtualization with SR-IOV. 1-10 - Dan Tang, Yungang Bao, Weiwu Hu, Mingyu Chen:
DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance. 1-12
System Architecture and Performance Evaluation
- Jason E. Miller, Harshad Kasture, George Kurian, Charles Gruenwald III, Nathan Beckmann, Christopher Celio, Jonathan Eastep, Anant Agarwal:
Graphite: A distributed parallel simulator for multicores. 1-12 - Davy Genbrugge, Stijn Eyerman, Lieven Eeckhout:
Interval simulation: Raising the level of abstraction in architectural simulation. 1-12 - Sajib Kundu, Raju Rangaswami, Kaushik Dutta, Ming Zhao:
Application performance modeling in a virtualized environment. 1-10 - Jaejin Lee, Jun Lee, Sangmin Seo, Jungwon Kim
COMIC++: A software SVM system for heterogeneous multicore accelerator clusters. 1-12
Processor Microarchitecture
- Andrew D. Hilton, Amir Roth:
BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution. 1-12 - Libo Huang, Li Shen, Zhiying Wang, Wei Shi, Nong Xiao, Sheng Ma:
SIF: Overcoming the limitations of SIMD devices via implicit permutation. 1-12 - Polychronis Xekalakis, Marcelo Cintra:
Handling branches in TLS systems with Multi-Path Execution. 1-12
Industrial Perspectives
- Arijit Biswas, Charles Recchia, Shubhendu S. Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Athanasios E. Papathanasiou, Mike Plaster, Norbert Seifert:
Explaining cache SER anomaly using DUE AVF measurement. 1-12 - Arunchandar Vasan, Anand Sivasubramaniam, Vikrant Shimpi, T. Sivabalan, Rajesh Subbiah:
Worth their watts? - an empirical study of datacenter servers. 1-10 - Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González:
High-Performance low-vcc in-order core. 1-11 - Malcolm S. Ware, Karthick Rajamani, Michael S. Floyd, Bishop Brock, Juan C. Rubio, Freeman L. Rawson III, John B. Carter:
Architecting for power management: The IBM POWER7TM approach. 1-11
Architectures for Emerging Technologies
- Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, Hsien-Hsin S. Lee:
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth. 1-12 - Yan Pan, John Kim
FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar. 1-12
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