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28th FCCM 2020: Fayetteville, AR, USA
- 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020, Fayetteville, AR, USA, May 3-6, 2020. IEEE 2020, ISBN 978-1-7281-5803-7
- Hiroki Nakahara, Zhiqiang Que, Wayne Luk:
High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. 1-9 - Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk:
Optimizing Reconfigurable Recurrent Neural Networks. 10-18 - Yuan Meng
, Sanmukh R. Kuppannagari
Accelerating Proximal Policy Optimization on CPU-FPGA Heterogeneous Platforms. 19-27 - Wentai Zhang
Evaluating Low-Memory GEMMs for Convolutional Neural Network Inference on FPGAs. 28-32 - Zhilin Xu, Jincheng Yu, Chao Yu, Hao Shen, Yu Wang, Huazhong Yang:
CNN-based Feature-point Extraction for Real-time Visual SLAM on Embedded FPGA. 33-37 - Alex Forencich, Alex C. Snoeren, George Porter, George Papen:
Corundum: An Open-Source 100-Gbps Nic. 38-46 - Juan Camilo Vega
FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark. 47-55 - Sunwoong Kim
Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme. 56-64 - Kaspar Matas
Power-hammering through Glitch Amplification - Attacks and Mitigation. 65-69 - Ian Elmor Lang, Ziqiang Huang, Nachiket Kapre:
Exploring The Impact Of Switch Arity On Butterfly Fat Tree Fpga Nocs. 70-74 - Lukas Sommer
Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. 75-83 - Martin Langhammer, Sergey Gribok, Gregg Baeckler:
High Density 8-Bit Multiplier Systolic Arrays For Fpga. 84-92 - S. Rasoul Faraji, Pierre Abillama
Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP Applications. 93-101 - Shulin Zeng, Guohao Dai, Hanbo Sun, Kai Zhong, Guangjun Ge, Kaiyuan Guo, Yu Wang, Huazhong Yang:
Enabling Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud. 102-110 - Zeke Wang, Hongjing Huang, Jie Zhang
Shuhai: Benchmarking High Bandwidth Memory On FPGAS. 111-119 - Eric Matthews, Yuhui Gao, Lesley Shannon:
Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors. 120-128 - Francesco Restuccia, Alessandro Biondi
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC. 129-137 - Reza Rahimi, Elaheh Sadredini
Grapefruit: An Open-Source, Full-Stack, and Customizable Automata Processing on FPGAs. 138-147 - Pouya Haghi
FP-AMG: FPGA-Based Acceleration Framework for Algebraic Multigrid Solvers. 148-156 - Michael Lo
Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. 157-166 - Mohamed Omran Matar, Mrinmoy Jana, Jeebak Mitra, Lutz Lampe, Mieszko Lis:
A Turbo Maximum-a-Posteriori Equalizer for Faster-than-Nyquist Applications. 167-171 - Shuang Wen, Guojie Luo:
FPGA-accelerated Automatic Alignment for Three-dimensional Tomography. 172-176 - Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Tim Todman:
Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies. 177-185 - Charles Lo, Paul Chow:
Hierarchical Modelling of Generators in Design-Space Exploration. 186-194 - Wesson Altoyan, Juan J. Alonso
Investigating Performance Losses in High-Level Synthesis for Stencil Computations. 195-203 - Bahar Asgari, Ramyad Hadidi, Hyesoon Kim:
Proposing a Fast and Scalable Systolic Array for Matrix Multiplication. 204 - Jannatun Naher, Clay Gloster, Christopher C. Doss, Shrikant S. Jadhav
An Automated Tool for Design Space Exploration of Matrix Vector Multiplication (MVM) Kernels Using OpenCL Based Implementation on FPGAs. 205 - Rashmi S. Agrawal, Lake Bu, Michel A. Kinsy:
Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption. 206 - Ayan Palchaudhuri
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability. 207 - João Carlos Resende, Ricardo J. R. Maçãs
TBOX-Based Mask Scrambling Against SCA. 208 - José Luis Imaña
FPGA Implementation of Post-Quantum DME Cryptosystem. 209 - Yukui Luo, Xiaolin Xu:
A Dynamic Frequency Scaling Framework Against Reliability and Security Issues in Multi-tenant FPGA. 210 - Juan Camilo Vega
SHIP: Storage for Hybrid Interconnected Processors. 211 - MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David:
RISC-V Barrel Processor for Accelerator Control. 212 - Chenglong Li
Update Latency Optimization of Packet Classification for SDN Switch on FPGA. 213 - Joel Mandebi Mbongue, Christophe Bobda:
Accommodating Multi-Tenant FPGAs in the Cloud. 214 - Qingqing Xiong, Chen Yang, Pouya Haghi
Accelerating MPI Collectives with FPGAs in the Network and Novel Communicator Support. 215 - Md Jubaer Hossain Pantho, Christophe Bobda:
MeXT-SE: A System-Level Design Tool to Transparently Generate Secure MPSoC. 216 - Parnian Mokri, Mark Hempstead:
Early-stage Automated Identification Tool for Shared Accelerators. 217 - Maria Angelica Davila Guzman, Ruben Gran Tejero
An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis. 218 - Ian D. Taras, Andrew G. Schmidt:
FPGA Virtualization for Deprecated Devices. 219 - Burkhard Ringlein
ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters. 220 - Anthony M. Cabrera, Roger D. Chamberlain:
Designing Domain Specific Computing Systems. 221 - Emmanuel Lesser:
Improving the Availability of Secure Space Links through the Partial Reconfiguration of FPGAs. 222 - Zhe Pan
An FPGA-Optimized Architecture of Real-time Farneback Optical Flow. 223 - Bashar Romanous, Mohammadreza Rezvani, Junjie Huang, Daniel Wong
High-Performance Parallel Radix Sort on FPGA. 224 - Haoyan Liu, Atiyehsadat Panahi, David Andrews
FPGA-Based Gesture Recognition with Capacitive Sensor Array using Recurrent Neural Networks. 225 - Oscar Ferraz
Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications. 226 - Ayokunle Fadamiro, Pouyan Rezaie, Christopher Harris, Spencer K. Millican:
A Quaternary FPGA Architecture Using Floating Gate Memories. 227 - Reza Nakhjavani, Jianwen Zhu:
Rotary Register File: A Micro-Architectural Primitive on FPGA. 228 - Akira Jinguji, Shimpei Sato, Hiroki Nakahara:
Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. 229 - Madis Kerner, Kalle Tammemäe, Jaan Raik, Thomas Hollstein:
An Efficient FPGA-based Architecture for Contractive Autoencoders. 230 - Akshay Dua, Yixing Li, Fengbo Ren:
Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing. 231 - Yanpeng Cao
Explore Efficient LUT-based Architecture for Quantized Convolutional Neural Networks on FPGA. 232 - Feng Yu, Yanpeng Cao
Realization of Quantized Neural Network for Super-resolution on PYNQ. 233 - Tamon Sadasue, Tsuyoshi Isshiki:
Scalable Full Hardware Logic Architecture for Gradient Boosted Tree Training. 234 - Alaa Maarouf, Nour El Droubi, Raghid Morcel, Hazem M. Hajj, Mazen A. R. Saghir, Haitham Akkary:
Optimized Distribution of an Accelerated Convolutional Neural Network across Multiple FPGAs. 235 - Panagiotis Mousouliotis, Ioannis Papaefstathiou
SqueezeJet-3: An Accelerator Utilizing FPGA MPSoCs for Edge CNN Applications. 236 - Dimitrios Danopoulos, Christoforos Kachris, Dimitrios Soudris
Automatic Generation of FPGA Kernels From Open Format CNN Models. 237 - Yaman Umuroglu, Yash Akhauri, Nicholas J. Fraser, Michaela Blott:
High-Throughput DNN Inference with LogicNets. 238 - Naif Tarafdar, Giuseppe Di Guglielmo, Philip C. Harris, Jeffrey D. Krupa, Vladimir Loncar, Dylan S. Rankin
AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters. 239 - Joshua Mack
FPGA Based High-Throughput Real-Time Feature Extraction for Modulation Classification. 240 - Bingyi Zhang, Hanqing Zeng, Viktor K. Prasanna:
Accelerating Large Scale GCN Inference on FPGA. 241 - Sathish Panchapakesan, Zhenman Fang, Nitin Chandrachoodan:
EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA. 242 - Ning Li, Leibo Liu, Shaojun Wei, Shouyi Yin:
A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNs. 243
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