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ARVLSI 1997: Ann Arbor, MI, USA
- 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA. IEEE Computer Society 1997, ISBN 0-8186-7913-1
- Daniel W. Dobberpuhl:
Circuits and Technology for Digital's StrongARM(tm) and ALPHA Microprocessors. 2-11 - David Parry:
Scalability in computing for today and tomorrow. 12-31 - V. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi:
Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity. 32-46 - Allen E. Sjogren, Chris J. Myers:
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline. 47-61 - Les Hall, Mark Clements, Wentai Liu, Griff L. Bilbro:
Clock Distribution Using Cooperative Ring Oscillators. 62-77 - B. Chester Hwang:
Trends of Key Advanced Device Technologies. 78-81 - Chandra Tan, Donald W. Bouldin, Peyman H. Dehkordi:
Design Implementation of Intrinsic Area Array ICs. 82-95 - Alejandro F. González, Pinaki Mazumder:
Compact Signed-Digit Adder Using Multiple-Valued Logic. 96-113 - Todd Hinck, Allyn E. Hubbard:
Image Edge Enhancement, Dynamic Compression and Noise Suppression using Analog Circuit Processing. 114-126 - George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis:
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. 127-144 - David M. Dahle, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Eric Rice, Don Speck, Douglas H. Williams, Richard Hughey:
Kestrel: Design of an 8-bit SIMD Parallel Processor. 145- - Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings:
The Design of an Asynchronous MIPS R3000 Microprocessor. 164-181 - Stephen P. DeWeerth, Girish N. Patel, Mario F. Simoni, David E. Schimmel, Ronald L. Calabrese:
A VLSI Architecture for Modeling Intersegmental Coordination. 182-200 - Hans M. Jacobson, Ganesh Gopalakrishnan:
Asynchronous Microengines for Efficient High-level Control. 201-218 - Martin Benes, Andrew Wolfe, Steven M. Nowick:
A High-Speed Asynchronous Decompression Circuit for Embedded Processors. 219-237 - Nathan Shnidman, William H. Mangione-Smith, Miodrag Potkonjak:
Fault Scanner for Reconfigurable Logic. 238-255 - Waleed Meleis, Miriam Leeser, Paul M. Zavracky, Mankuan Michael Vai:
Architectural Design of a Three Dimensional FPGA. 256-269 - Behzad Razavi:
Next-Generation RF Circuits and Systems. 270-283 - Kevin J. Nowka
, H. Peter Hofstee:
Circuits and Microarchitecture for Gigahertz VLSI Designs. 284-287 - John Poulton:
An Embedded DRAM for CMOS ASICs. 288-302 - Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun:
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors. 303-319
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