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39th MICRO 2006: Orlando, Florida, USA
- 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA. IEEE Computer Society 2006, ISBN 0-7695-2732-9
Reliability and Bug Detection
- Fayez Mohamood, Michael B. Healy, Sung Kyu Lim
, Hsien-Hsin S. Lee:
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. 3-14 - Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou:
Yield-Aware Cache Architectures. 15-25 - Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas:
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware. 26-37 - Shan Lu
PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection. 38-52
Compiler and Branch Handling
- Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt:
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. 53-64 - Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley:
Merging Head and Tail Duplication for Convergent Hyperblock Formation. 65-76 - Mark Heffernan, Kent D. Wilken, Ghassan Shobaki
Data-Dependency Graph Transformations for Superblock Scheduling. 77-88 - Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley:
Dataflow Predication. 89-102
Security
- Weidong Shi, Hsien-Hsin S. Lee:
Authentication Control Point and Its Implications For Secure Processor Design. 103-112 - Xiaotong Zhuang, Tao Zhang, Santosh Pande
Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection. 113-122 - Kun Zhang, Tao Zhang, Santosh Pande
Memory Protection through Dynamic Access Control. 123-134 - Feng Qin, Cheng Wang, Zhenmin Li, Ho-Seop Kim, Yuanyuan Zhou, Youfeng Wu:
LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks. 135-148
Superscalar Processors
- Ron Gabor, Shlomo Weiss, Avi Mendelson:
Fairness and Throughput in Switch on Event Multithreading. 149-160 - P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil:
A Predictive Performance Model for Superscalar Processors. 161-170 - Anne Bracy, Amir Roth:
Serialization-Aware Mini-Graphs: Performance with Fewer Resources. 171-184
Memory Systems
- Bratin Saha, Ali-Reza Adl-Tabatabai, Quinn Jacobson:
Architectural Support for Software Transactional Memory. 185-196 - Banit Agrawal, Timothy Sherwood
Virtually Pipelined Network Memory. 197-207 - Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, James E. Smith:
Fair Queuing Memory Systems. 208-222
CMP Execution
- Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe:
Reunion: Complexity-Effective Multicore Redundancy. 223-234 - Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder:
Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. 235-246 - Pierre Palatin, Yves Lhuillier, Olivier Temam:
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs. 247-258 - Ram Rangan, Neil Vachharajani, Adam Stoler, Guilherme Ottoni, David I. August, George Z. N. Cai:
Support for High-Frequency Streaming in CMPs. 259-272
Memory Dependences
- Samantika Subramaniam, Gabriel H. Loh:
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All. 273-284 - Tingting Sha, Milo M. K. Martin, Amir Roth:
NoSQ: Store-Load Communication without a Store Queue. 285-296 - Fernando Castro
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering. 297-308
Networks and Coherence
- Michael R. Marty, Mark D. Hill:
Coherence Ordering for Ring-based Chip Multiprocessors. 309-320 - Noel Eisley, Li-Shiuan Peh, Li Shang:
In-Network Cache Coherence. 321-332 - Chrysostomos Nicopoulos
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. 333-346
Power
- Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi:
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. 347-358 - Canturk Isci, Gilberto Contreras, Margaret Martonosi:
Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management. 359-370 - Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry:
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units. 371-384
Caches and Prefetching
- Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh:
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads. 385-396 - Ibrahim Hur, Calvin Lin:
Memory Prefetching Using Adaptive Stream Detection. 397-408 - James Tuck, Luis Ceze, Josep Torrellas:
Scalable Cache Miss Handling for High Memory-Level Parallelism. 409-422
Managing CMP Caches
- Moinuddin K. Qureshi, Yale N. Patt:
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. 423-432 - Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell:
Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. 433-442 - Bradford M. Beckmann, Michael R. Marty, David A. Wood:
ASR: Adaptive Selective Replication for CMP Caches. 443-454 - Sangyeun Cho, Lei Jin:
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. 455-468
Technology-Driven Architecture
- Bryan Black, Murali Annavaram
Die Stacking (3D) Microarchitecture. 469-479 - Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. 480-491 - Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. 492-503 - Xiaoyao Liang, David M. Brooks:
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units. 504-514
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