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"A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using ..."

Jiawei Wang et al. (2024)

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DOI: 10.1109/TCSII.2023.3335987

access: closed

type: Journal Article

metadata version: 2024-04-15

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  - https://dblp.org/rec/journals/tcasII/WangGCWLHZ24
Jiawei Wang, Zhao Gao, Xu Cheng, Jue Wang, Zhen Li, Jun Han, Xiaoyang Zeng:
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1859-1863 (2024)

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