default search action

combined dblp search
author search
venue search
publication search

ask others

"Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin ..."

Christoph Albrecht et al. (2002)

> Home

Details and statistics

DOI: 10.1109/ASPDAC.2002.994986

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/AlbrechtKMZ02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/AlbrechtKMZ02
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. ASP-DAC/VLSI Design 2002: 580-

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.