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"Power-Clock Gating in Adiabatic Logic Circuits."

Philip Teichmann et al. (2005)

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DOI: 10.1007/11556930_65

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/patmos/TeichmannFHAS05
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  - https://dblp.org/rec/conf/patmos/TeichmannFHAS05
Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel:
Power-Clock Gating in Adiabatic Logic Circuits. PATMOS 2005: 638-646

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