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"A High-Performance SRAM Technology With Reduced Chip-Level Routing ..."

R. Castagnetti et al. (2005)

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DOI: 10.1109/ISQED.2005.6

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/isqed/CastagnettiVBMBTR05
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  - https://dblp.org/rec/conf/isqed/CastagnettiVBMBTR05
R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh:
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. ISQED 2005: 193-196

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