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Manoj Franklin
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- affiliation: University of Maryland, College Park, USA
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2020 – today
- 2020
- [c58]Xinyu Zhou, Manoj Franklin:
Indoor Route and Location Inference using Smartphone IMU Sensors. PIMRC 2020: 1-7
2010 – 2019
- 2011
- [c57]Michael David Black, Manoj Franklin:
Teaching computer architecture with a graphical PC simulator. ITiCSE 2011: 337 - 2010
- [c56]Rania H. Mameesh, Manoj Franklin:
Speculative-aware execution: a simple and efficient technique for utilizing multi-cores to improve single-thread performance. PACT 2010: 421-430
2000 – 2009
- 2008
- [j12]Joonhyuk Yoo
, Manoj Franklin:
Hierarchical Verification for Increasing Performance in Reliable Processors. J. Electron. Test. 24(1-3): 117-128 (2008) - [c55]Jizhu Lu, Michael Perrone, Kursad Albayraktaroglu, Manoj Franklin:
HMMer-Cell: High Performance Protein Profile Searching on the Cell/B.E. Processor. ISPASS 2008: 223-232 - 2007
- [j11]Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj Franklin:
Non-Inclusion Property in Multi-Level Caches Revisited. Int. J. Comput. Their Appl. 14(2): 99-108 (2007) - [c54]Joonhyuk Yoo, Manoj Franklin:
Prioritizing verification via value-based correctness criticality. ICCD 2007: 333-340 - 2006
- [c53]Mohamed M. Zahran, Manoj Franklin:
RHT: A Context-Based Return Address Predictor. CDES 2006: 17-23 - [c52]Joonhyuk Yoo, Manoj Franklin:
The Filter Checker: An Active Verification Management Approach. DFT 2006: 516-524 - [c51]Sean Leventhal, Manoj Franklin:
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors. ICCD 2006: 148-154 - 2005
- [j10]Aneesh Aggarwal, Manoj Franklin:
Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency. IEEE Trans. Computers 54(12): 1496-1507 (2005) - [j9]Aneesh Aggarwal, Manoj Franklin:
Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors. IEEE Trans. Parallel Distributed Syst. 16(10): 944-955 (2005) - [c50]Michael D. Black, Manoj Franklin:
Neural Confidence Estimation for More Accurate Value Prediction. HiPC 2005: 376-385 - [c49]Rania H. Mameesh, Manoj Franklin:
SST: Symbolic Subordinate Threading. ICCD 2005: 662-665 - [c48]Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Manoj Franklin, Bruce L. Jacob, Chau-Wen Tseng, Donald Yeung:
BioBench: A Benchmark Suite of Bioinformatics Applications. ISPASS 2005: 2-9 - 2004
- [j8]Anasua Bhowmik, Manoj Franklin:
A General Compiler Framework for Speculative Multithreaded Processors. IEEE Trans. Parallel Distributed Syst. 15(8): 713-724 (2004) - [c47]Aneesh Aggarwal, Manoj Franklin, Oguz Ergin
Defining Wakeup Width for Efficient Dynamic Scheduling. ICCD 2004: 36-41 - 2003
- [c46]Aneesh Aggarwal, Manoj Franklin:
Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency. IEEE PACT 2003: 46-55 - [c45]Aneesh Aggarwal, Manoj Franklin:
Energy Efficient Asymmetrically Ported Register Files. ICCD 2003: 2-7 - [c44]Mohamed M. Zahran, Manoj Franklin:
Dynamic Thread Resizing for Speculative Multithreaded Processors. ICCD 2003: 313- - [c43]Anasua Bhowmik, Manoj Franklin:
A fast approximate interprocedural analysis for speculative multithreading compilers. ICS 2003: 32-41 - [c42]Renju Thomas, Manoj Franklin, Chris Wilkerson, Jared Stark:
Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History. ISCA 2003: 314-323 - 2002
- [c41]Krishnan Kailas
A Register File Architecture and Compilation Scheme for Clustered ILP Processors. Euro-Par 2002: 500-511 - [c40]Anasua Bhowmik, Manoj Franklin:
Exploiting Data Value Prediction in Compiler Based Thread Formation. HiPC 2002: 506-518 - [c39]Renju Thomas, Manoj Franklin:
Using Dataflow Based Contextfor Accurate Branch Prediction. HiPC 2002: 587-596 - [c38]Mohamed M. Zahran
Return-Address Prediction in Speculative Multithreaded Environments. HiPC 2002: 609-619 - [c37]Aneesh Aggarwal, Manoj Franklin:
Hierarchical Interconnects for On-Chip Clustering. IPDPS 2002 - [c36]Mohamed M. Zahran
A Feasibility Study of Hierarchical Multithreading. IPDPS 2002 - [c35]Anasua Bhowmik, Manoj Franklin:
A general compiler framework for speculative multithreading. SPAA 2002: 99-108 - 2001
- [c34]Renju Thomas, Manoj Franklin:
Using Dataflow Based Context for Accurate Value Prediction. IEEE PACT 2001: 107-117 - [c33]Aneesh Aggarwal, Manoj Franklin:
Putting Data Value Predictors to Work in Fine-Grain Parallel Processors. HiPC 2001: 204-213 - [c32]Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, André Seznec:
Boosting SMT Performance by Speculation Control. IPDPS 2001: 2 - [c31]Kun Luo, Jayanth Gummaraju, Manoj Franklin:
Balancing thoughput and fairness in SMT processors. ISPASS 2001: 164-171 - [c30]Aneesh Aggarwal, Manoj Franklin:
An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors. ISPASS 2001: 172-179 - 2000
- [c29]Jayanth Gummaraju, Manoj Franklin:
Branch Prediction in Multi-Threaded Processors. IEEE PACT 2000: 179-188
1990 – 1999
- 1999
- [j7]Simonjit Dutta, Manoj Franklin:
Control Flow Prediction Schemes for Wide-Issue Superscalar Processors. IEEE Trans. Parallel Distributed Syst. 10(4): 346-359 (1999) - [c28]Wamsi Mohan, Manoj Franklin:
Improving Data Value Prediction Accuracy Using Path Correlation. HiPC 1999: 28-32 - [c27]Sreenivas Vadlapatla, Manoj Franklin:
Performance Benefits of Exploiting Control Independence. HiPC 1999: 33-37 - 1998
- [j6]Rahul Sathe, Kai Wang, Manoj Franklin:
Techniques for performing highly accurate data value prediction. Microprocess. Microsystems 22(6): 303-313 (1998) - [j5]Narayan Ranganathan, Manoj Franklin:
The PEWs microarchitecture: reducing complexity through data-dependence based decentralization. Microprocess. Microsystems 22(6): 333-343 (1998) - [c26]Narayan Ranganathan, Manoj Franklin:
An Empirical Study of Decentralized ILP Execution Models. ASPLOS 1998: 272-281 - [c25]Rahul Sathe, Manoj Franklin:
Available parallelism with data value prediction. HiPC 1998: 194-201 - [c24]Brian Toone, Manoj Franklin:
Control flow prediction with unbalanced tree-like subgraphs. HiPC 1998: 221-227 - 1997
- [c23]Kai Wang, Manoj Franklin:
Highly accurate data value prediction. HiPC 1997: 358-363 - [c22]Krishna K. Sundararaman, Manoj Franklin:
Multiscalar Execution along a Single Flow of Control. ICPP 1997: 106-113 - [c21]Kai Wang, Manoj Franklin:
Highly Accurate Data Value Prediction Using Hybrid Predictors. MICRO 1997: 281-290 - 1996
- [j4]Manoj Franklin, Gurindar S. Sohi:
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. IEEE Trans. Computers 45(5): 552-571 (1996) - [j3]Manoj Franklin, Kewal K. Saluja:
Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1081-1087 (1996) - [c20]Manoj Franklin:
Incorporating fault tolerance in superscalar processors. HiPC 1996: 301-306 - [c19]Vamsee K. Madavarapu, Manoj Franklin, Krishna K. Sundararaman:
A study of dynamic scheduling techniques for multiscalar processors. HiPC 1996: 413-418 - [c18]Gregory A. Kemp, Manoj Franklin:
PEWs: A Decentralized Dynamic Scheduler for ILP Processing. ICPP, Vol. 1 1996: 239-246 - 1995
- [c17]Manoj Franklin:
Fast computation of C-MISR signatures. Asian Test Symposium 1995: 293-297 - [c16]Manoj Franklin:
A study of time redundant fault tolerance techniques for superscalar processors. DFT 1995: 207-215 - [c15]Manoj Franklin:
Incorporating Fault Tolerance in the Multiscalar Fine-Grain Parallel Processor. ICPP (1) 1995: 110-117 - [c14]Mark Smotherman, Manoj Franklin:
Improving CISC instruction decoding performance using a fill unit. MICRO 1995: 219-229 - [c13]Simonjit Dutta, Manoj Franklin:
Control flow prediction with tree-like subgraphs for superscalar processors. MICRO 1995: 258-263 - [c12]Manoj Franklin, Kewal K. Saluja, Kyuchull Kim:
Fast computation of MISR signatures. VLSI Design 1995: 414-418 - 1994
- [j2]Manoj Franklin, Kewal K. Saluja:
Hypergraph Coloring and Reconfigured RAM Testing. IEEE Trans. Computers 43(6): 725-736 (1994) - [c11]Manoj Franklin, Mark Smotherman:
A fill-unit approach to multiple instruction issue. MICRO 1994: 162-171 - [c10]Manoj Franklin, Kewal K. Saluja:
An Algorithm to Test Reconfigured RAMs. VLSI Design 1994: 359-364 - 1993
- [c9]Dionisios N. Pnevmatikatos
Control flow prediction for dynamic ILP processors. MICRO 1993: 153-163 - 1992
- [c8]Manoj Franklin, Gurindar S. Sohi:
The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. ISCA 1992: 58-67 - [c7]Manoj Franklin, Gurindar S. Sohi:
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. MICRO 1992: 236-245 - 1991
- [c6]Gurindar S. Sohi, Manoj Franklin:
High-Bandwidth Data Memory Systems for Superscalar Processors. ASPLOS 1991: 53-62 - [c5]Manoj Franklin, Kewal K. Saluja:
Pattern Sensitive Fault Testing of RAMs with Bullt-in ECC. FTCS 1991: 385-392 - [c4]Manoj Franklin, Kewal K. Saluja:
An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults. ITC 1991: 675-684 - 1990
- [j1]Manoj Franklin, Kewal K. Saluja:
Built-in Self-testing of Random-Access Memories. Computer 23(10): 45-56 (1990)
1980 – 1989
- 1989
- [c3]Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita:
Row/column pattern sensitive fault detection in RAMs via built-in self-test. FTCS 1989: 36-43 - [c2]Gurindar S. Sohi, Manoj Franklin, Kewal K. Saluja:
A study of time-redundant fault tolerance techniques for high-performance pipelined computers. FTCS 1989: 436-443 - [c1]Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita:
Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. ITC 1989: 327-336
Coauthor Index
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