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Takashi Kobayashi 0002
Person information
- affiliation (since 1986): Hitachi Ltd., Central Research Laboratory, Tokyo, Japan
Other persons with the same name
- Takashi Kobayashi — disambiguation page
- Takashi Kobayashi 0001
— Tokyo Institute of Technology, Department of Computer Science, Japan (and 2 more)
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2000 – 2009
- 2007
- [j7]Kazuo Otsuga, Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi:
Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories. IEICE Trans. Electron. 90-C(4): 772-778 (2007) - [j6]Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume, Kazuki Homma, Teruhiko Ito, Yoshinori Sakamoto, Masahiro Shimizu, Yoshinori Ikeda, Osamu Tsuchiya, Kazunori Furusawa:
A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology. IEICE Trans. Electron. 90-C(11): 2146-2156 (2007) - 2006
- [j5]Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Keiichi Yoshida, Yoshinori Takase, Takayuki Yoshitake, Osamu Tsuchiya, Yoshinori Ikeda, Shunichi Narumi, Michitaro Kanamitsu, Kazuto Izawa, Kazunori Furusawa:
A 130-nm CMOS 95-mm2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput. IEICE Trans. Electron. 89-C(10): 1469-1479 (2006) - 2005
- [j4]Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara
Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories. IEEE J. Solid State Circuits 40(2): 523-531 (2005)
1990 – 1999
- 1999
- [j3]Kazuo Yano, Tomoyuki Ishii, Toshiaki Sano, Toshiyuki Mine, Fumio Murai, Takashi Hashimoto, Takashi Kobayashi, Tokuo Kure, Koichi Seki:
Single-electron memory for giga-to-tera bit storage. Proc. IEEE 87(4): 633-651 (1999) - 1998
- [j2]Takayuki Kawahara
Internal voltage generator for low voltage, quarter-micrometer flash memories. IEEE J. Solid State Circuits 33(1): 126-132 (1998) - 1996
- [j1]Takayuki Kawahara
Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. IEEE J. Solid State Circuits 31(11): 1590-1600 (1996) - 1991
- [c1]Takashi Kobayashi, Kenzo Kurihara:
Performance Model of Interference Avoidance Policy Using Stochastic Petri Nets. PNPM 1991: 125-133
Coauthor Index
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