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Daniele Baldi
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2020 – today
- 2020
- [c11]Enrico Sentieri, Tino Copani, Andrea Paganini, Matteo Traldi, Angelo Palladino, Antonio Santipo, Lorenzo Gerosa, Matteo Repossi, Gianluca Catrini, Marta Campo, Francesco Radice, Andrea Diodato, Roberto Pelleriti, Daniele Baldi, Laura Tarantini, Luca Maggi, Gianluca Radaelli, Stefano Cervini, Francesco Clerici, Angelo Moroni:
12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications. ISSCC 2020: 210-212
2010 – 2019
- 2016
- [j6]Enrico Temporiti, Andrea Ghilioni, Gabriele Minoia
, Piero Orlandi, Matteo Repossi
Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures. IEEE J. Solid State Circuits 51(12): 3178-3191 (2016) - [c10]Dan Li, Gabriele Minoia
A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links. ISCAS 2016: 2334-2337 - [c9]Enrico Temporiti, Gabriele Minoia
23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies. ISSCC 2016: 404-405 - 2015
- [c8]Marco Cignoli, Gabriele Minoia
22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s. ISSCC 2015: 1-3 - 2014
- [j5]Dan Li, Gabriele Minoia
A Low-Noise Design Technique for High-Speed CMOS Optical Receivers. IEEE J. Solid State Circuits 49(6): 1437-1447 (2014) - [c7]Enrico Temporiti, Gabriele Minoia
A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies. ESSCIRC 2014: 131-134 - [c6]Nicolo Sabatino, Gabriele Minoia
A 5th order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS. ESSCIRC 2014: 351-354 - 2012
- [c5]Dan Li, Gabriele Minoia
A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4. ESSCIRC 2012: 221-224 - 2010
- [j4]Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Marco Cusmai, Francesco Svelto:
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation. IEEE J. Solid State Circuits 45(12): 2723-2736 (2010) - [j3]Colin Weltin-Wu, Enrico Temporiti, Marco Cusmai, Daniele Baldi, Francesco Svelto:
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2259-2268 (2010) - [c4]Massimo Pozzoni, Simone Erba, Davide Sanzogni, Marcello Ganzerli, Paolo Viola, Daniele Baldi, Matteo Repossi
A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization. ISSCC 2010: 164-165 - [c3]Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Marco Cusmai, Francesco Svelto:
A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. ISSCC 2010: 468-469
2000 – 2009
- 2009
- [j2]Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. IEEE J. Solid State Circuits 44(3): 824-834 (2009) - [j1]Massimo Pozzoni, Simone Erba, Paolo Viola, Matteo Pisati, Emanuele Depaoli, Davide Sanzogni, Riccardo Brama, Daniele Baldi, Matteo Repossi
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication. IEEE J. Solid State Circuits 44(4): 1306-1315 (2009) - [c2]Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
Insights into wideband fractional All-Digital PLLs for RF applications. CICC 2009: 37-44 - 2008
- [c1]Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Francesco Svelto:
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction. ISSCC 2008: 344-345
Coauthor Index
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