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Julio Villalba
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2020 – today
- 2024
- [i1]Gerardo Bandera, Javier Salamero, Miquel Moretó, Julio Villalba:
Floating Point HUB Adder for RISC-V Sargantana Processor. CoRR abs/2401.09464 (2024) - 2022
- [j23]Julio Villalba, Javier Hormigo
:
High-Radix Formats for Enhancing Floating-Point FPGA Implementations. Circuits Syst. Signal Process. 41(3): 1683-1703 (2022) - 2020
- [c34]Javier Hormigo, Julio Villalba-Moreno, Sonia Gonzalez-Navarro
Floating-Point Fused Multiply-Add under HUB Format. ARITH 2020: 1-8
2010 – 2019
- 2019
- [j22]Julio Villalba
Fast HUB Floating-Point Adder for FPGA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(6): 1028-1032 (2019) - [c33]Julio Villalba-Moreno, Javier Hormigo, Francisco J. Jaime:
Reproducible Summation Under HUB Format. ARITH 2019: 38-45 - 2018
- [j21]Julio Villalba-Moreno
Unbiased Rounding for HUB Floating-Point Addition. IEEE Trans. Computers 67(9): 1359-1365 (2018) - 2017
- [j20]Javier Hormigo
Introduction to the Special Issue on Computer Arithmetic. IEEE Trans. Computers 66(12): 1991-1993 (2017) - [j19]Javier Hormigo, Julio Villalba:
HUB Floating Point for Improving FPGA Implementations of DSP Applications. IEEE Trans. Circuits Syst. II Express Briefs 64-II(3): 319-323 (2017) - [c32]Julio Villalba-Moreno, Javier Hormigo:
Floating Point Square Root under HUB Format. ICCD 2017: 447-454 - 2016
- [j18]Javier Hormigo
New Formats for Computing with Real-Numbers under Round-to-Nearest. IEEE Trans. Computers 65(7): 2158-2168 (2016) - [j17]Carlos Garcia-Vega
Decimal Multiformat Online Addition. IEEE Trans. Computers 65(10): 3203-3209 (2016) - [j16]Javier Hormigo
Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2369-2377 (2016) - [c31]Julio Villalba-Moreno:
Digit Recurrence Floating-Point Division under HUB Format. ARITH 2016: 79-86 - 2015
- [c30]Javier Hormigo
Simplified floating-point units for high dynamic range image and video systems. ISCE 2015: 1-2 - 2014
- [c29]Javier Hormigo
Optimizing DSP circuits by a new family of arithmetic operators. ACSSC 2014: 871-875 - 2013
- [j15]Javier Hormigo
Multioperand Redundant Adders on FPGAs. IEEE Trans. Computers 62(10): 2013-2025 (2013) - [c28]Julio Villalba
Efficient floating-point representation for balanced codes for FPGA devices. ICCD 2013: 272-277 - 2012
- [j14]Julio Villalba, Tomás Lang, Javier Hormigo
Radix-2 Multioperand and Multiformat Streaming Online Addition. IEEE Trans. Computers 61(6): 790-803 (2012) - [j13]Álvaro Vázquez, Julio Villalba-Moreno
Redundant Floating-Point Decimal CORDIC Algorithm. IEEE Trans. Computers 61(11): 1551-1562 (2012) - [c27]Carlos Garcia-Vega
Decimal online multioperand addition. ACSCC 2012: 350-354 - [c26]Carlos Garcia-Vega, Sonia González-Navarro
On-line Decimal Adder with RBCD Representation. ASAP 2012: 53-60 - 2011
- [j12]Francisco J. Jaime
High-Speed Algorithms and Architectures for Range Reduction Computation. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 512-516 (2011) - 2010
- [j11]Francisco J. Jaime
Enhanced Scaling-Free CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1654-1662 (2010) - [c25]Francisco J. Quiles, Manuel Ortiz
UCORE: Reconfigurable Platform for Educational Purposes. ReConFig 2010: 109-114
2000 – 2009
- 2009
- [c24]Álvaro Vázquez, Julio Villalba
Computation of Decimal Transcendental Functions Using the CORDIC Algorithm. IEEE Symposium on Computer Arithmetic 2009: 179-186 - [c23]Javier Hormigo
Efficient Implementation of Carry-Save Adders in FPGAs. ASAP 2009: 207-210 - [c22]Carlos Diego Moreno-Moreno
Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator. ICECS 2009: 419-422 - 2008
- [j10]Elisardo Antelo
A Low-Latency Pipelined 2D and 3D CORDIC Processors. IEEE Trans. Computers 57(3): 404-417 (2008) - [j9]Francisco J. Jaime
Pipelined Architecture for Additive Range Reduction. J. Signal Process. Syst. 53(1-2): 103-112 (2008) - [c21]Francisco J. Jaime
SIMD Enhancements for a Hough Transform Implementation. DSD 2008: 899-903 - [c20]Francisco J. Jaime
New SIMD instructions set for image processing applications enhancement. ICIP 2008: 1396-1399 - 2007
- [c19]Julio Villalba, Javier Hormigo, Tomás Lang:
Improving the Throughput of On-line Addition for Data Streams. ASAP 2007: 272-277 - 2006
- [j8]Joaquín Olivares
SAD computation based on online arithmetic for motion estimation. Microprocess. Microsystems 30(5): 250-258 (2006) - [j7]Julio Villalba
Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations. IEEE Trans. Computers 55(3): 254-267 (2006) - [c18]Francisco J. Jaime
Pipelined Range Reduction for Floating Point Numbers. ASAP 2006: 145-152 - [c17]Joaquín Olivares
Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. FPL 2006: 1-4 - 2005
- [c16]Elisardo Antelo, Julio Villalba:
Low Latency Pipelined Circular CORDIC. IEEE Symposium on Computer Arithmetic 2005: 280-287 - [c15]Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata:
On-line Multioperand Addition Based on On-line Full Adders. ASAP 2005: 322-327 - 2004
- [j6]Javier Hormigo
CORDIC Processor for Variable-Precision Interval Arithmetic. J. VLSI Signal Process. 37(1): 21-39 (2004) - [c14]Joaquín Olivares
Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. FPL 2004: 986-990 - [c13]Gerardo Bandera, Mario A. González, Julio Villalba, Javier Hormigo, Emilio L. Zapata:
Evaluation of Elementary Functions Using Multimedia Features. IPDPS 2004 - 2002
- [c12]Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo
Polynomial Evaluation on Multimedia Processors. ASAP 2002: 265- - 2000
- [c11]Javier Hormigo, Julio Villalba, Michael J. Schulte:
A Hardware Algorithm for Variable-Precision Logarithm. ASAP 2000: 215-224 - [c10]Julio Villalba, Javier Hormigo, Mario A. González, Emilio L. Zapata:
MMX-Like Architecture Extension to Support the Rotation Operation. IEEE International Conference on Multimedia and Expo (III) 2000: 1383-1386
1990 – 1999
- 1999
- [c9]Javier Hormigo
Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. IEEE Symposium on Computer Arithmetic 1999: 186-193 - [c8]Javier Hormigo
Arithmetic Unit for the Computation of Interval Elementary Functions. EUROMICRO 1999: 1063-1066 - 1998
- [j5]Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
Radix-4 Vectoring CORDIC Algorithm and Architectures. J. VLSI Signal Process. 19(2): 127-147 (1998) - [j4]Julio Villalba, Tomás Lang, Emilio L. Zapata:
Parallel Compensation of Scale Factor for the CORDIC Algorithm. J. VLSI Signal Process. 19(3): 227-241 (1998) - [c7]Javier Hormigo, Julio Villalba, Emilio L. Zapata:
A Hardware Approach to Interval Arithmetic for Sine and Cosine Functions. SCAN 1998: 31-41 - 1997
- [j3]Elisardo Antelo
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46(8): 855-870 (1997) - [c6]Julio Villalba, Tomás Lang:
Low latency word serial CORDIC. ASAP 1997: 124-131 - 1996
- [j2]Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata:
Cordic based parallel/pipelined architecture for the Hough transform. J. VLSI Signal Process. 12(3): 207-221 (1996) - [c5]Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP 1996: 55-64 - [c4]Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata:
High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II 1996: 155-164 - 1995
- [j1]Nicolás Guil, Julio Villalba
A fast Hough transform for segment detection. IEEE Trans. Image Process. 4(11): 1541-1548 (1995) - [c3]Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata:
Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic 1995: 172-179 - [c2]Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata:
Digit On-line Large Radix CORDIC Rotator. ASAP 1995: 246-257 - [c1]Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP 1995: 258-269
Coauthor Index
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