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Dan B. Kasha

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2006
[j3]
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Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore:
A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. IEEE J. Solid State Circuits 41(12): 2930-2944 (2006)
1999
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Dan B. Kasha, Wai L. Lee, Axel Thomsen:
A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing. IEEE J. Solid State Circuits 34(7): 921-926 (1999)
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Axel Thomsen, Dan B. Kasha, Lei Wang, Wai L. Lee:
A 110-dB-THD, 18-mW DAC using sampling of the output and feedback to reduce distortion. IEEE J. Solid State Circuits 34(12): 1733-1740 (1999)

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