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Chia-Sheng Wen
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2010 – 2019
- 2017
- [j5]Shen-Fu Hsiao
, Chia-Sheng Wen, Yi-Hau Chen, Kuei-Chun Huang:
Hierarchical Multipartite Function Evaluation. IEEE Trans. Computers 66(1): 89-99 (2017) - 2015
- [j4]Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher:
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(5): 466-470 (2015) - 2014
- [c8]Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu:
Compression of Lookup Table for Piecewise Polynomial Function Evaluation. DSD 2014: 279-284 - 2013
- [j3]Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen:
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 875-886 (2013) - [c7]Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen:
Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units. VLSI-DAT 2013: 1-4 - 2012
- [j2]Shen-Fu Hsiao, Hou-Jen Ko, Chia-Sheng Wen:
Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions. IEEE Trans. Circuits Syst. II Express Briefs 59-II(5): 292-296 (2012) - [c6]Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen:
Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system. APCCAS 2012: 408-411 - [c5]Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Andrew Lee:
Low-cost designs of rectangular to polar coordinate converters for digital communication. APCCAS 2012: 511-514 - 2010
- [j1]Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen:
Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 21-25 (2010) - [c4]Shen-Fu Hsiao, Chia-Sheng Wen, Kun-Chih Chen
Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method. APCCAS 2010: 1079-1082
2000 – 2009
- 2008
- [c3]Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen:
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. ISCAS 2008: 2022-2025 - 2006
- [c2]Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen:
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. APCCAS 2006: 1631-1634 - 2005
- [c1]Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen:
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. ISCAS (3) 2005: 2433-2436
Coauthor Index
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