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Yong Liu 0023
Person information
- affiliation (2015 - 2016): Shanghai Jiao Tong University, China
- affiliation (2007 - 2015): IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
- affiliation (PhD 2007): Harvard University, Cambridge, MA, USA
- affiliation (1996 - 2003): Tsinghua University, Beijing, China
Other persons with the same name
- Yong Liu — disambiguation page
- Yong Liu 0001
— Outreach Corporation, Seattle, WA, USA (and 3 more)
- Yong Liu 0002
- Yong Liu 0003
- Yong Liu 0004
- Yong Liu 0005
- Yong Liu 0006
- Yong Liu 0007
- Yong Liu 0008
- Yong Liu 0009
- Yong Liu 0010
- Yong Liu 0011
- Yong Liu 0012
- Yong Liu 0013
- Yong Liu 0014 — Texas A&M University, College Station, USA
- Yong Liu 0015 — Nottingham Trent University, UK
- Yong Liu 0016
- Yong Liu 0017
- Yong Liu 0018
- Yong Liu 0019
- Yong Liu 0020
- Yong Liu 0021
- Yong Liu 0022
- Yong Liu 0024 — Indiana University, Department of Computer Science, Bloomington, IN, USA
- Yong Liu 0025 — Northwestern Polytechnical University, College of Automation, Xi'an, China
- Yong Liu 0026
- Yong Liu 0027 — Beijing University of Posts and Telecommunications, School of Information and Communication Engineering, Beijing Key Laboratory of Network System Architecture and Convergence, China
- Yong Liu 0028 — Chongqing Jiaotong University, School of Economics and Management, Chongqing, China
- Yong Liu 0029
- Yong Liu 0030
- Yong Liu 0031
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2010 – 2019
- 2016
- [j8]Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman:
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. IEEE J. Solid State Circuits 51(8): 1744-1755 (2016) - [c12]Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli:
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. ISSCC 2016: 56-57 - 2015
- [j7]Timothy O. Dickson, Yong Liu, Sergey V. Rylov
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 50(8): 1917-1931 (2015) - [c11]Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman:
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. CICC 2015: 1-4 - 2014
- [c10]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC 2014: 1-4 - 2013
- [c9]Yong Liu, Ping-Hsuan Hsieh
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. ISSCC 2013: 400-401 - 2012
- [j6]Timothy O. Dickson, Yong Liu, Sergey V. Rylov
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. IEEE J. Solid State Circuits 47(4): 884-896 (2012) - [j5]Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman:
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. IEEE J. Solid State Circuits 47(12): 3220-3231 (2012) - [c8]Nan Sun, Yong Liu, Ling Qin, Guangyu Xu
Solid-state and biological systems interface. ESSCIRC 2012: 14-17 - [c7]Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman:
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. ISSCC 2012: 134-136 - [c6]Yong Liu, Wing K. Luk, Daniel J. Friedman:
A compact low-power 3D I/O in 45nm CMOS. ISSCC 2012: 142-144 - 2011
- [c5]Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. CICC 2011: 1-4
2000 – 2009
- 2009
- [j4]Nan Sun, Yong Liu, Hakho Lee
CMOS RF Biosensor Utilizing Nuclear Magnetic Resonance. IEEE J. Solid State Circuits 44(5): 1629-1643 (2009) - [j3]Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman:
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. IEEE J. Solid State Circuits 44(12): 3526-3538 (2009) - [c4]Yong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman:
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. ISSCC 2009: 182-183 - 2008
- [j2]Kyoungho Woo, Yong Liu, Eunsoo Nam, Donhee Ham
Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Differing Bandwidths. IEEE J. Solid State Circuits 43(2): 379-389 (2008) - [c3]Yong Liu, Nan Sun, Hakho Lee
CMOS Mini Nuclear Magnetic Resonance System and its Application for Biomolecular Sensing. ISSCC 2008: 140-141 - 2007
- [c2]Yong Liu, Woogeun Rhee
All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs. ISSCC 2007: 176-595 - 2006
- [j1]Hakho Lee
IC/microfluidic hybrid system for magnetic manipulation of biological cells. IEEE J. Solid State Circuits 41(6): 1471-1480 (2006) - 2002
- [c1]Yong Liu, Zhiqiang Gao, Xiangqing He:
A Flexible Embedded SRAM Compiler. DELTA 2002: 474-476
Coauthor Index
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