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Kari Tiensyrjä
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2010 – 2019
- 2013
- [j5]Janne Vatjus Anttila, Jari Kreku, Juha Korpi, Subayal Khan, Jukka Saastamoinen, Kari Tiensyrjä:
Early-phase performance exploration of embedded systems with ABSOLUT framework. J. Syst. Archit. 59(10-D): 1128-1143 (2013) - 2011
- [c21]Jukka Saastamoinen, Subayal Khan, Kari Tiensyrjä, Tapio Taipale:
Multi-threading support for system-level performance simulation of multi-core architectures. ARCS Workshops 2011 - [c20]Subayal Aftab Khan, Jukka Saastamoinen, Kari Tiensyrjä, Jari Nurmi
:
System Level Performance Simulation of Distributed GENESYS Applications on Multi-core Platforms. DASC 2011: 313-320 - 2010
- [c19]Jari Kreku, Kari Tiensyrjä, Geert Vanmeerbeeck:
Automatic workload generation for system-level exploration based on modified GCC compiler. DATE 2010: 369-374 - [c18]Subayal Khan, Kari Tiensyrjä, Jari Nurmi
Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile. DSD 2010: 251-254 - [c17]Subayal Khan, Eila Ovaska
From Y-chart to seamless integration of application design and performance simulation. SoC 2010: 18-25 - [c16]Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch
The MOSART Mapping Optimization for Multi-Core ARchiTectures. ISVLSI (Selected papers) 2010: 181-195 - [c15]Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch
Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. ISVLSI 2010: 518-523
2000 – 2009
- 2009
- [c14]Subayal Khan, Susanna Pantsar-Syväniemi, Jari Kreku, Kari Tiensyrjä, Juha-Pekka Soininen:
Linking GENESYS application architecture modelling with platform performance simulation. FDL 2009: 1-6 - 2008
- [j4]Jari Kreku, Mika Hoppari, Tuomo Kestilä, Yang Qu, Juha-Pekka Soininen, Per Andersson, Kari Tiensyrjä:
Combining UML2 Application and SystemC Platform Modelling for Performance Evaluation of Real-Time Embedded Systems. EURASIP J. Embed. Syst. 2008 (2008) - [j3]Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi
Design Flow Instantiation for Run-Time Reconfigurable Systems: A Case Study. EURASIP J. Embed. Syst. 2008 (2008) - [c13]Jari Kreku, Mika Hoppari, Tuomo Kestilä, Yang Qu, Juha-Pekka Soininen, Kari Tiensyrjä:
Application - Platform Performance Modeling and Evaluation. FDL 2008: 43-48 - [c12]Jari Kreku, Mika Hoppari, Tuomo Kestilä, Yang Qu, Juha-Pekka Soininen, Kari Tiensyrjä:
Application Workload and SystemC Platform Modeling for Performance Evaluation. FDL (Selected Papers) 2008: 131-147 - 2007
- [c11]Jari Kreku, Mika Hoppari, Kari Tiensyrjä, Per Andersson:
SystemC workload model generation from UML for performance simulation. FDL 2007: 204-285 - [c10]Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi
System-Level Design for Partially Reconfigurable Hardware. ISCAS 2007: 2738-2741 - 2006
- [c9]Jari Kreku, Yang Qu, Juha-Pekka Soininen, Kari Tiensyrjä:
Layered UML Workload and SystemC Platform Models. FDL 2006: 223-229 - [c8]Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo:
System Level Architecture Exploration for Reconfigurable Systems On Chip. FPL 2006: 1-6 - 2005
- [c7]Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen:
SystemC-based Design Methodology for Reconfigurable System-on-Chip. DSD 2005: 364-371 - 2004
- [c6]Kari Tiensyrjä, Miroslav Cupák, Kostas Masselos, Marko Pettissalo:
SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip. FDL 2004: 428-440 - [c5]Yang Qu, Kari Tiensyrjä, Kostas Masselos:
System-Level Modeling of Dynamically Reconfigurable Co-processors. FPL 2004: 881-885 - 2002
- [c4]Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani:
A Network on Chip Architecture and Design Methodology. ISVLSI 2002: 117-124
1990 – 1999
- 1997
- [c3]Sien-An Ong, Kari Tiensyrjä, Lech Józwiak:
Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models. EUROMICRO 1997: 172-181 - 1995
- [c2]Juha-Pekka Soininen, Tuomo Huttunen, Kari Tiensyrjä, Hannu Heusala:
Cosimulation of real-time control systems. EURO-DAC 1995: 170-175 - 1994
- [c1]Matti Kärkkäinen, Kari Tiensyrjä, Matti Weissenfelt:
Boundary Scan Testing Combined with Power Supply Current Monitoring. EDAC-ETC-EUROASIC 1994: 232-235
1980 – 1989
- 1989
- [j2]Juha-Pekka Soininen, Matti Sipola, Kari Tiensyrjä:
SW/HW-partitioning of real-time embedded systems. Microprocessing and Microprogramming 27(1-5): 239-244 (1989) - 1988
- [j1]Timo Juntunen, Jorma Kivelä, Auli Reinikka, Matti Sipola, Juha-Pekka Soininen, Kari Tiensyrjä, Tuomo Tikkanen:
Real-time structured analysis in system level design of embedded ASICs. Microprocess. Microprogramming 24(1-5): 449-454 (1988)
Coauthor Index
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