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Alin Razafindraibe
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2010 – 2019
- 2011
- [i1]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback. CoRR abs/1103.1360 (2011)
2000 – 2009
- 2008
- [c9]Sumanta Chaudhuri
, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98 - 2007
- [c8]Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri
A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT 2007: 369-372 - [c7]Alin Razafindraibe, Michel Robert
Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. PATMOS 2007: 340-351 - [c6]Alin Razafindraibe, Philippe Maurine:
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. PATMOS 2007: 394-403 - [c5]Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet:
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22 - [c4]Alin Razafindraibe, Michel Robert, Philippe Maurine:
Improvement of dual rail logic as a countermeasure against DPA. VLSI-SoC 2007: 270-275 - 2006
- [c3]Alin Razafindraibe, Michel Robert, Philippe Maurine:
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. PATMOS 2006: 634-644 - [c2]Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin:
Security evaluation of dual rail logic against DPA attacks. VLSI-SoC 2006: 181-186 - 2005
- [j1]Alin Razafindraibe, Michel Robert, Philippe Maurine:
Compact and Secured Primitives for the Design of Asynchronous Circuits. J. Low Power Electron. 1(1): 20-26 (2005) - [c1]Alin Razafindraibe, Michel Robert
A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS 2005: 571-580
Coauthor Index
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