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Mahyar Emami
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2020 – today
- 2024
- [c7]Sahand Kashani
, Mahyar Emami
A 475 MHz Manycore FPGA Accelerator for RTL Simulation. FPGA 2024: 78-84 - [c6]Jiacheng Ma, Rishabh R. Iyer, Sahand Kashani, Mahyar Emami, Thomas Bourgeat, George Candea:
Performance Interfaces for Hardware Accelerators. OSDI 2024: 855-874 - [i3]Mahyar Emami, Thomas Bourgeat, James R. Larus:
Parendi: Thousand-Way Parallel RTL Simulation. CoRR abs/2403.04714 (2024) - 2023
- [c5]Mahyar Emami
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism. ASPLOS (4) 2023: 219-237 - [i2]Mahyar Emami, Sahand Kashani, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus:
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism. CoRR abs/2301.09413 (2023) - 2022
- [c4]Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus:
Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks. PACT 2022: 398-411 - [c3]Sahand Kashani, Mahyar Emami, James R. Larus:
Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats. FPL 2022: 1-8 - 2021
- [c2]Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus:
Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems. FPGA 2021: 226-227 - [i1]Endri Bezati, Mahyar Emami, Jörn W. Janneck, James R. Larus:
StreamBlocks: A compiler for heterogeneous dataflow computing (technical report). CoRR abs/2107.09333 (2021) - 2020
- [c1]Endri Bezati, Mahyar Emami, James R. Larus:
Advanced Dataflow Programming using Actor Machines for High-Level Synthesis. FPGA 2020: 310
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