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Simon Van Beek
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2020 – today
- 2024
- [c14]Farrukh Yasin, A. Palomino, A. Kumar, Valerio Pica, Simon Van Beek, Giacomo Talmelli, V. D. Nguyen, Stefan Cosemans, D. Crotti, Kurt Wostyn, Gouri Sankar Kar, Sebastien Couet:
Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c13]Fernando García-Redondo
, S. Rao, M. Gupta, Manu Perumkunnil, Y. Xiang, D. Abdi, Simon Van Beek, S. Couet, Marie Garcia Bardon:
STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes. ESSDERC 2023: 97-100 - [c12]Simon Van Beek, Kaiming Cai, Kaiquan Fan, Giacomo Talmelli, Anna Trovato, Nico Jossart, Siddharth Rao, Adrian Vaisman Chasin, Sebastien Couet:
MTJ degradation in multi-pillar SOT-MRAM with selective writing. IRPS 2023: 1-7 - 2022
- [c11]Simon Van Beek, Kaiming Cai
MTJ degradation in SOT-MRAM by self-heating-induced diffusion. IRPS 2022: 4 - [c10]Kaiming Cai, Simon Van Beek, Siddharth Rao, K. Fan
Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories. VLSI Technology and Circuits 2022: 375-376 - 2021
- [c9]Sidharth Rao
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. IMW 2021: 1-4 - [c8]Simon Van Beek, Siddharth Rao
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. IRPS 2021: 1-5 - 2020
- [c7]Simon Van Beek, Barry J. O'Sullivan, Sebastien Couet
Understanding and empirical fitting the breakdown of MgO in end-of-line annealed MTJs. IRPS 2020: 1-5
2010 – 2019
- 2019
- [c6]Erik Bury, Adrian Vaisman Chasin, Michiel Vandemaele, Simon Van Beek, Jacopo Franco, Ben Kaczer, Dimitri Linten:
Array-Based Statistical Characterization of CMOS Degradation Modes and Modeling of the Time-Dependent Variability Induced by Different Stress Patterns in the {VG, VD} bias space. IRPS 2019: 1-6 - 2018
- [c5]Simon Van Beek, Philippe Roussel, Barry J. O'Sullivan, Robin Degraeve, Stefan Cosemans, Dimitri Linten, Gouri Sankar Kar:
Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit. ESSDERC 2018: 146-149 - [c4]Erik Bury, Ben Kaczer, Simon Van Beek, Dimitri Linten:
Experimental extraction of BEOL composite equivalent thermal conductivities for application in self-heating simulations. ESSDERC 2018: 186-189 - [c3]Barry J. O'Sullivan, Simon Van Beek, Philippe J. Roussel, Sidharth Rao
Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown. IRPS 2018: 5-1 - [c2]Kevin Garello, Kevin Garello Yasin, S. Couet, Laurent Souriau
SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories. VLSI Circuits 2018: 81-82 - [i1]Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar:
SOT-MRAM 300mm integration for low power and ultrafast embedded memories. CoRR abs/1810.10356 (2018) - 2015
- [c1]Simon Van Beek, Koen Martens, Philippe Roussel, Gabriele Luca Donadio, Johan Swerts, Sofie Mertens, Gouri Sankar Kar, Tai Min, Guido Groeseneken
Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions. IRPS 2015: 4
Coauthor Index
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