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Zhenxin Zhao
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2020 – today
- 2024
- [j5]Zhenxin Zhao, Jun Liu, Lihong Zhang:
Acceleration for Efficient Automated Generation of Operational Amplifiers. Sensors 24(12): 3990 (2024) - 2023
- [j4]Zhenxin Zhao, Jiang Luo, Jun Liu, Lihong Zhang:
Signal-Division-Aware Analog Circuit Topology Synthesis Aided by Transfer Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3481-3490 (2023) - 2022
- [j3]Zhenxin Zhao, Lihong Zhang:
Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5138-5151 (2022) - [c8]Zhenxin Zhao, Lihong Zhang:
Deep Reinforcement Learning for Analog Circuit Structure Synthesis. DATE 2022: 1157-1160 - [c7]Mohammad Hajijafari, Mehrnaz Ahmadi, Zhenxin Zhao, Lihong Zhang:
Fogging-Effect-Aware Mixed-Signal IC Placement with Reinforcement Learning. ISCAS 2022: 2895-2899 - [c6]Mohammad Hajijafari, Mehrnaz Ahmadi, Zhenxin Zhao, Lihong Zhang:
Reinforcement-Learning-based Mixed-Signal IC Placement for Fogging Effect Control. ISQED 2022: 127-132 - 2021
- [j2]Zhenxin Zhao, Lihong Zhang:
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1824-1837 (2021) - 2020
- [j1]Zhenxin Zhao, Lihong Zhang:
An Automated Topology Synthesis Framework for Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4325-4337 (2020) - [c5]Lian He, Zhenxin Zhao, Yuanzhu Chen, Lihong Zhang:
Placement with Sequence-Pair-Driven TCG for Advanced Analog Constraints. CCECE 2020: 1-4 - [c4]Lian He, Zhenxin Zhao, Yuanzhu Chen, Lihong Zhang:
Advanced Transitive-Closure-Graph-Based Placement Representation for Analog Layout Design. ICECS 2020: 1-4 - [c3]Zhenxin Zhao, Lihong Zhang:
Deep Reinforcement Learning for Analog Circuit Sizing. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c2]Zhenxin Zhao, Lihong Zhang:
Graph-Grammar-Based Analog Circuit Topology Synthesis. ISCAS 2019: 1-5 - 2018
- [c1]Zhenxin Zhao, Tuotian Liao, Lihong Zhang:
Fast Performance Evaluation for Analog Circuit Synthesis Frameworks. ISCAS 2018: 1-5
Coauthor Index
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last updated on 2024-07-20 20:33 CEST by the dblp team
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