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Cyril Prasanna Raj
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2020 – today
- 2020
- [j3]S. S. Divakara, Sudarshan Patilkulkarni
, Cyril Prasanna Raj:
Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic. Int. J. Image Graph. 20(3): 2050017:1-2050017:19 (2020)
2010 – 2019
- 2018
- [j2]S. S. Divakara, Sudarshan Patilkulkarni
High Speed Area Optimized Hybrid DA Architecture for 2D-DTCWT. Int. J. Image Graph. 18(1): 1850004:1-1850004:21 (2018) - 2017
- [j1]S. S. Divakara, Sudarshan Patilkulkarni
High speed modular systolic array-based DTCWT with parallel processing architecture for 2D image transformation on FPGA. Int. J. Wavelets Multiresolution Inf. Process. 15(5): 1750047:1-1750047:16 (2017) - 2010
- [c6]B. M. Sunil, Cyril Prasanna Raj:
Analysis of Wavelet for 3D-DWT Volumetric Image Compression. ICETET 2010: 180-185 - [c5]K. V. Venkata Ramanaiah, Cyril Prasanna Raj:
VLSI Architecuture for Neural Network Based Image Compression. ICETET 2010: 749-754 - [c4]Y. N. Santhosh, Namita Palacha, Cyril Prasanna Raj:
Design and VLSI Implementation of Interpolators/Decimators for DUC/DDC. ICETET 2010: 755-759 - [c3]A. Ravi Kumar, Cyril Prasanna Raj, G. M. Sree Rama Reddy:
Design and Verification of Cache Memory Decoder for High Speed Multicore Processor. ICETET 2010: 770-775 - [c2]M. B. Veena
FPGA Based Reconfigurable 200 MHz Transmitter and Receiver Front End for MIMO-OFDM. ICETET 2010: 819-824
2000 – 2009
- 2009
- [c1]Pachara V. Rao, Cyril Prasanna Raj, S. Ravi
VLSI Design and Analysis of Multipliers for Low Power. IIH-MSP 2009: 1354-1357
Coauthor Index
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