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Hao-Yu Chi
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2020 – today
- 2023
- [j3]A. K. Thasreefa
, Abhishek Patyal
On Reducing LDE Variations in Modern Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1268-1279 (2023) - [c10]Kai-Shun Hu, Hao-Yu Chi, I-Jye Lin, Yi-Hsuan Wu, Wei-Hsu Chen, Yi-Ting Hsieh:
Invited Paper: 2023 ICCAD CAD Contest Problem B: 3D Placement with Macros. ICCAD 2023: 1-6 - 2022
- [c9]Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho:
Practical Substrate Design Considering Symmetrical and Shielding Routes. DATE 2022: 951-956 - [c8]Kai-Shun Hu, I-Jye Lin, Yu-Hui Huang, Hao-Yu Chi, Yi-Hsuan Wu, Cindy Chin-Fang Shen:
2022 ICCAD CAD Contest Problem B: 3D Placement with D2D Vertical Connections. ICCAD 2022: 94:1-94:5 - 2021
- [j2]Hao-Yu Chi
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(12): 2556-2567 (2021) - [c7]Hao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Liu, Jing-Yang Jou:
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design. DATE 2021: 1218-1223 - 2020
- [j1]Hao-Yu Chi, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Wire Load Oriented Analog Routing with Matching Constraints. ACM Trans. Design Autom. Electr. Syst. 25(6): 55:1-55:26 (2020) - [c6]Mark Po-Hung Lin
Achieving Analog Layout Integrity through Learning and Migration Invited Talk. ICCAD 2020: 55:1-55:8
2010 – 2019
- 2019
- [c5]Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines. ICCAD 2019: 1-6 - [c4]Yu-Hsien Chen, Hao-Yu Chi, Ling-Yen Song, Chien-Nan Jimmy Liu, Hung-Ming Chen:
A Structure-Based Methodology for Analog Layout Generation. SMACD 2019: 33-36 - 2018
- [c3]Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Performance-preserved analog routing methodology via wire load reduction. ASP-DAC 2018: 482-487 - [c2]Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu:
Analog placement with current flow and symmetry constraints using PCP-SP. DAC 2018: 10:1-10:6 - 2017
- [c1]Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu:
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering. VLSI-DAT 2017: 1-4
Coauthor Index
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