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Haruyoshi Yonekawa
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2010 – 2019
- 2019
- [j2]Hiroki Nakahara
, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato:
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. 102-D(5): 1003-1011 (2019) - 2018
- [j1]Kota Ando
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53(4): 983-994 (2018) - [c8]Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato:
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. FPGA 2018: 31-40 - [c7]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. ISMVL 2018: 174-179 - 2017
- [c6]Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura:
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). FPGA 2017: 290 - [c5]Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato:
A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. FPL 2017: 1 - [c4]Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato:
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. FPT 2017: 168-175 - [c3]Haruyoshi Yonekawa, Hiroki Nakahara:
On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA. IPDPS Workshops 2017: 98-105 - [c2]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS 2017: 116-119 - 2016
- [c1]Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
A memory-based realization of a binarized deep convolutional neural network. FPT 2016: 277-280
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