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Thomas B. Rolinger
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2020 – today
- 2024
- [j2]Qiang Fu, Yuede Ji, Thomas B. Rolinger, H. Howie Huang
:
TLPGNN: A Lightweight Two-level Parallelism Paradigm for Graph Neural Network Computation on Single and Multiple GPUs. ACM Trans. Parallel Comput. 11(2): 7 (2024) - [c15]Qiang Fu, Thomas B. Rolinger, H. Howie Huang
JITSPMM: Just-in-Time Instruction Generation for Accelerated Sparse Matrix-Matrix Multiplication. CGO 2024: 448-459 - [c14]Thomas B. Rolinger, Alan Sussman:
Adaptive Prefetching for Fine-grain Communication in PGAS Programs. IPDPS 2024: 740-751 - 2023
- [b1]Thomas B. Rolinger:
Compiler Optimizations for Irregular Memory Access Patterns in the PGAS Programming Model. University of Maryland, College Park, MD, USA, 2023 - [c13]Ahsen J. Uppal, Thomas B. Rolinger, H. Howie Huang
Decontentioned Stochastic Block Partition. HPEC 2023: 1-6 - [i5]Thomas B. Rolinger, Christopher D. Krieger, Alan Sussman:
Compiler Optimization for Irregular Memory Access Patterns in PGAS Programs. CoRR abs/2303.13954 (2023) - [i4]Qiang Fu, Thomas B. Rolinger, H. Howie Huang
JITSPMM: Just-in-Time Instruction Generation for Accelerated Sparse Matrix-Matrix Multiplication. CoRR abs/2312.05639 (2023) - 2022
- [c12]Thomas B. Rolinger, Christopher D. Krieger, Alan Sussman:
Compiler Optimization for Irregular Memory Access Patterns in PGAS Programs. LCPC 2022: 3-21 - 2021
- [c11]Ahsen J. Uppal, Jaeseok Choi, Thomas B. Rolinger, H. Howie Huang
Faster Stochastic Block Partition Using Aggressive Initial Merging, Compressed Representation, and Parallelism Control. HPEC 2021: 1-7 - [c10]Thomas B. Rolinger, Christopher D. Krieger, Alan Sussman
Optimizing Memory-Compute Colocation for Irregular Applications on a Migratory Thread Architecture. IPDPS 2021: 58-67 - [c9]Thomas B. Rolinger, Joseph Craft, Christopher D. Krieger, Alan Sussman
Towards High Productivity and Performance for Irregular Applications in Chapel. SC (Workshops) 2021: 1-11 - 2020
- [c8]Kaushik Velusamy, Thomas B. Rolinger, Janice McMahon:
Performance Strategies for Parallel Bitonic Sort on a Migratory Thread Architecture. HPEC 2020: 1-7
2010 – 2019
- 2019
- [j1]Thomas B. Rolinger
Performance considerations for scalable parallel tensor decomposition. J. Parallel Distributed Comput. 129: 83-98 (2019) - [c7]Thomas B. Rolinger, Christopher D. Krieger, Alan Sussman
Optimizing Data Layouts for Irregular Applications on a Migratory Thread Architecture. MCHPC@SC 2019: 7-15 - 2018
- [c6]Thomas B. Rolinger
An Empirical Evaluation of Allgatherv on Multi-GPU Systems. CCGrid 2018: 123-132 - [c5]Kaushik Velusamy, Thomas B. Rolinger
Exploring Parallel Bitonic Sort on a Migratory Thread Architecture. HPEC 2018: 1-7 - [c4]Thomas B. Rolinger
Parallel Sparse Tensor Decomposition in Chapel. IPDPS Workshops 2018: 896-905 - [c3]Thomas B. Rolinger
Impact of Traditional Sparse Optimizations on a Migratory Thread Architecture. IA3@SC 2018: 45-52 - [i3]Thomas B. Rolinger, Christopher D. Krieger:
Impact of Traditional Sparse Optimizations on a Migratory Thread Architecture. CoRR abs/1812.05955 (2018) - [i2]Thomas B. Rolinger, Tyler A. Simon, Christopher D. Krieger:
Parallel Sparse Tensor Decomposition in Chapel. CoRR abs/1812.05961 (2018) - [i1]Thomas B. Rolinger, Tyler A. Simon, Christopher D. Krieger:
An Empirical Evaluation of Allgatherv on Multi-GPU Systems. CoRR abs/1812.05964 (2018) - 2017
- [c2]Thomas B. Rolinger
Performance challenges for heterogeneous distributed tensor decompositions. HPEC 2017: 1-7 - 2016
- [c1]Thomas B. Rolinger
Performance Evaluation of Parallel Sparse Tensor Decomposition Implementations. IA3@SC 2016: 54-57
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last updated on 2024-10-07 21:16 CEST by the dblp team
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