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Matthias Mutz
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1990 – 1999
- 1999
- [c9]Matthias Mutz, Sebastian Steibl:
Formale Verifikation der Architekturverbesserung eines Viterbi Decoder IP Blocks. MBMV 1999: 61-70 - [e1]Matthias Mutz, Nikolaus Lange:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Braunschweig, Germany, February 22-24, 1999. Shaker 1999 [contents] - 1998
- [j1]Werner Grass, Thomas Kropf, Matthias Mutz:
Formale Methoden bei der Spezifikation von Hardware. Informationstechnik Tech. Inform. 40(3): 13-17 (1998) - [c8]Matthias Mutz:
Register Transfer Level VHDL Models without Clocks. DATE 1998: 153-158 - [c7]Thomas Lock, Michael Mendler, Matthias Mutz:
Combined Formal Post- and Presynthesis Verification in High Level Synthesis. FMCAD 1998: 222-236 - [c6]Nikolaus Lange, Matthias Mutz:
Formale Verifikation eines funktionalen VHDL Modells der J1850 Busarbitrierung. MBMV 1998: 67-74 - 1997
- [c5]Matthias Mutz:
Automatic post-synthesis verification support for a high level synthesis step by using the HOL theorem proving system. CHARME 1997: 291-308 - 1994
- [c4]Matthias Mutz:
An automatically verified generalized multifunction arithmetic pipeline. EURO-DAC 1994: 290-295 - 1993
- [b1]Matthias Mutz:
Formale Beschreibung und automatisierte Verifikation von sequentiellem Hardwareverhalten auf der Basis von Logik höherer Ordnung. University of Passau, Germany, Shaker 1993, ISBN 978-3-86111-668-4, pp. 1-262 - 1992
- [c3]Matthias Mutz:
Verification of digital circuits based on formal semantics of a hardware description language. EURO-DAC 1992: 98-103 - 1991
- [c2]Matthias Mutz:
Using the HOL Prove Assistant for proving the Correctness of term Rewriting Rules reducing Terms of Sequential Behavior. CAV 1991: 277-287
1980 – 1989
- 1988
- [c1]Werner Grass, Matthias Mutz:
Modulare Implementierung von Schaltwerken unter Berücksichtigung topologischer Randbedingungen. GI Jahrestagung (2) 1988: 160-173
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