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Jeroen van Straten
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2020 – today
- 2023
- [c11]Yongding Tian
, Matthijs A. Reukers
Tydi-lang: A Language for Typed Streaming Hardware. SC Workshops 2023: 520-529 - [c10]Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
An Intermediate Representation for Composable Typed Streaming Dataflow Designs. VLDB Workshops 2023 - [i3]Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
An Intermediate Representation for Composable Typed Streaming Dataflow Designs. CoRR abs/2308.13436 (2023) - 2022
- [i2]Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
Tydi-lang: A Language for Typed Streaming Hardware. CoRR abs/2212.06259 (2022) - 2021
- [j5]Johan Peltenburg
Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow. J. Signal Process. Syst. 93(5): 565-586 (2021) - 2020
- [j4]Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee:
Tydi: An Open Specification for Complex Data Structures Over Hardware Streams. IEEE Micro 40(4): 120-130 (2020)
2010 – 2019
- 2019
- [j3]Joost Hoozemans
Frame-based Programming, Stream-Based Processing for Medical Image Processing Applications. J. Signal Process. Syst. 91(1): 47-59 (2019) - [j2]Joost Hoozemans
ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA. J. Signal Process. Syst. 91(1): 61-73 (2019) - [c9]Johan Peltenburg, Jeroen van Straten
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow. ARC 2019: 32-47 - [c8]Johan Peltenburg, Jeroen van Straten
Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow. FPL 2019: 270-277 - [c7]Xiang Fu, Leon Riesebos
eQASM: An Executable Quantum Instruction Set Architecture. HPCA 2019: 224-237 - 2018
- [j1]Joost Hoozemans, Jeroen van Straten, Stephan Wong:
Increasing resource utilization in mixed-criticality systems using a polymorphic VLIW processor. J. Syst. Archit. 84: 2-11 (2018) - [c6]Joost Hoozemans, Jeroen van Straten, Zaid Al-Ars, Stephan Wong:
Evaluating Auto-adaptation Methods for Fine-Grained Adaptable Processors. ARCS 2018: 255-268 - [i1]Xiang Fu, Leon Riesebos, M. A. Rol, Jeroen van Straten, J. van Someren, Nader Khammassi, Imran Ashraf, R. F. L. Vermeulen, V. Newsum, K. K. L. Loh, J. C. de Sterke, W. J. Vlothuizen, R. N. Schouten, Carmen G. Almudéver, Leonardo DiCarlo, Koen Bertels:
eQASM: An Executable Quantum Instruction Set Architecture. CoRR abs/1808.02449 (2018) - 2017
- [c5]Joost Hoozemans, Rolf Heij, Jeroen van Straten
VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications. ARC 2017: 36-43 - [c4]Anthony Brandon, Joost Hoozemans, Jeroen van Straten
Exploring ILP and TLP on a Polymorphic VLIW Processor. ARCS 2017: 177-189 - [c3]Joost Hoozemans, Jeroen van Straten
Using a polymorphic VLIW processor to improve schedulability and performance for mixed-criticality systems. RTCSA 2017: 1-9 - 2015
- [c2]Anthony Brandon, Joost Hoozemans, Jeroen van Straten
A sparse VLIW instruction encoding scheme compatible with generic binaries. ReConFig 2015: 1-7 - [c1]Joost Hoozemans, Jens Johansen, Jeroen van Straten
Multiple contexts in a multi-ported VLIW register file implementation. ReConFig 2015: 1-6
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