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Shounak Chakraborty 0001
Person information
- affiliation: Norwegian University of Science and Technology (NTNU), Trondheim, Norway
- affiliation: Indian Institute of Information Technology Guwahati, Department of Computer Science and Engineering, Assam, India
- not to be confused with: Shounak Chakraborty 0002
Other persons with the same name
- Shounak Chakraborty 0002
— Indian Institute of Information Technology Guwahati, Department of Computer Science and Engineering, Assam, India
- Shounak Chakraborty 0003 — Max Planck Institute for Informatics, Saarbrücken, Germany
- Shounak Chakraborty 0004 — Indian Institute of Information Technology Design and Manufacturing, Kurnool, India
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2020 – today
- 2024
- [j11]Sangeet Saha
ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 2944-2957 (2024) - [j10]Shounak Chakraborty
TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores. ACM Trans. Embed. Comput. Syst. 23(4): 61:1-61:31 (2024) - [c16]Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier:
MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. DAC 2024: 92:1-92:6 - [c15]Sukarn Agarwal, Shounak Chakraborty, Magnus Själander:
TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. IPDPS 2024: 852-864 - 2023
- [j9]Sangeet Saha
DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. IEEE Trans. Parallel Distributed Syst. 34(2): 718-733 (2023) - [c14]Sukarn Agarwal, Shounak Chakraborty, Magnus Själander
Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). DAC 2023: 1-6 - [c13]Shounak Chakraborty, Mehdi Safarpour, Olli Silvén:
NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems. SAMOS 2023: 33-42 - 2022
- [j8]Sangeet Saha
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5246-5260 (2022) - [j7]Yanshul Sharma, Shounak Chakraborty, Sanjay Moulik
ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms. J. Supercomput. 78(8): 1-25 (2022) - [c12]Shounak Chakraborty, Vassos Soteriou, Magnus Själander
STIFF: thermally safe temperature effect inversion aware FinFET based multi-core. CF 2022: 21-29 - [c11]Yanshul Sharma, Sanjay Moulik
RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore. DATE 2022: 608-611 - 2021
- [j6]Sanjay Moulik
SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorEReal-time Systems. J. Syst. Archit. 114: 101953 (2021) - [j5]Shounak Chakraborty, Magnus Själander
WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption. ACM Trans. Archit. Code Optim. 18(4): 55:1-55:25 (2021) - [j4]Shounak Chakraborty, Sangeet Saha, Magnus Själander
Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. ACM Trans. Embed. Comput. Syst. 20(5s): 62:1-61:25 (2021) - [c10]Sukarn Agarwal
ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. ASAP 2021: 171-174 - 2020
- [c9]Shounak Chakraborty, Sangeet Saha, Magnus Själander
RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress. CODES+ISSS 2020: 8-10
2010 – 2019
- 2019
- [j3]Shounak Chakraborty, Hemangee K. Kapoor:
Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design. ACM Trans. Design Autom. Electr. Syst. 24(5): 52:1-52:28 (2019) - 2018
- [j2]Shounak Chakraborty
Analysing the Role of Last Level Caches in Controlling Chip Temperature. IEEE Trans. Sustain. Comput. 3(4): 289-305 (2018) - [c8]Ashwini A. Kulkarni
Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors. ACM Great Lakes Symposium on VLSI 2018: 249-254 - 2017
- [j1]Shounak Chakraborty, Hemangee K. Kapoor:
Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs. Microprocess. Microsystems 52: 221-235 (2017) - [c7]Shounak Chakraborty, Hemangee K. Kapoor:
Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors. VLSID 2017: 75-80 - 2016
- [c6]Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs. SAC 2016: 1739-1744 - [c5]Shounak Chakraborty, Hemangee K. Kapoor:
Static energy reduction by performance linked dynamic cache resizing. VLSI-SoC 2016: 1-6 - 2015
- [c4]Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. IPDPS Workshops 2015: 444-453 - [c3]Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty:
Static energy reduction by performance linked cache capacity management in tiled CMPs. SAC 2015: 1913-1918 - [c2]Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Power aware cache miss reduction by energy efficient victim retention. VDAT 2015: 1-6 - 2014
- [c1]Narendra Kumar Meena, Hemangee K. Kapoor, Shounak Chakraborty:
A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip. VDAT 2014: 1-6
Coauthor Index
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