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Andrew Bitar
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2020 – today
- 2022
- [c10]Dennis Abts, Ibrahim Ahmed, Andrew Bitar, Matthew Boyd, John Kim, Garrin Kimmell, Andrew C. Ling:
Challenges/Opportunities to Enable Dependable Scale-out System with Groq Deterministic Tensor-Streaming Processors. DSN (Supplements) 2022: 19-22 - [c9]Dennis Abts, John Kim, Garrin Kimmell, Matthew Boyd, Kris Kang, Sahil Parmar, Andrew C. Ling, Andrew Bitar, Ibrahim Ahmed, Jonathan Ross:
The Groq Software-defined Scale-out Tensor Streaming Multiprocessor : From chips-to-systems architectural overview. HCS 2022: 1-69 - [c8]Dennis Abts, Garrin Kimmell, Andrew C. Ling, John Kim, Matthew Boyd, Andrew Bitar, Sahil Parmar, Ibrahim Ahmed, Roberto DiCecco, David Han, John Thompson, Michael Bye, Jennifer Hwang, Jeremy Fowers, Peter Lillian, Ashwin Murthy, Elyas Mehtabuddin, Chetan Tekur, Thomas Sohmers, Kris Kang, Stephen Maresh, Jonathan Ross:
A software-defined tensor streaming multiprocessor for large-scale machine learning. ISCA 2022: 567-580
2010 – 2019
- 2018
- [c7]Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu:
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. FPL 2018: 411-418 - [c6]Andrew C. Ling, Mohamed S. Abdelfattah, Shane O'Connell, Andrew Bitar, David Han, Roberto DiCecco, Suchit Subhaschandra, Chris N. Johnson, Dmitry Denisenko, Joshua Fender, Gordon R. Chiu:
Harnessing Numerical Flexibility for Deep Learning on FPGAs. HEART 2018: 1:1-1:3 - [c5]Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah:
Flexibility: FPGAs and CAD in Deep Learning Acceleration. ISPD 2018: 34-41 - [i1]Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu:
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. CoRR abs/1807.06434 (2018) - 2017
- [j1]Mohamed S. Abdelfattah
, Andrew Bitar, Vaughn Betz:
Design and Applications for Embedded Networks-on-Chip on FPGAs. IEEE Trans. Computers 66(6): 1008-1021 (2017) - 2015
- [c4]Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz:
Take the Highway: Design for Embedded NoCs on FPGAs. FPGA 2015: 98-107 - [c3]Mohamed S. Abdelfattah, Andrew Bitar, Ange Yaghi, Vaughn Betz:
Design and simulation tools for Embedded NOCs on FPGAs. FPL 2015: 1 - [c2]Andrew Bitar, Mohamed S. Abdelfattah, Vaughn Betz:
Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA. FPT 2015: 24-31 - 2014
- [c1]Andrew Bitar, Jeffrey Cassidy, Natalie D. Enright Jerger
Efficient and programmable ethernet switching with a NoC-enhanced FPGA. ANCS 2014: 89-100
Coauthor Index
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