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Shingo Yoshizawa
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2020 – today
- 2023
- [j25]Shingo Yoshizawa, Hiroshi Tsutsui:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 454-455 (2023) - [c47]Yuki Yamada, Shingo Yoshizawa, Takashi Saito, Hideki Sugimoto:
Iterative Variable Threshold Method Resistant to Acoustic Reflections for Underwater Acoustic Positioning Systems. ISCIT 2023: 224-225 - 2021
- [c46]Etou Hiromu, Shingo Yoshizawa:
Automatic Discrimination of Sound Propagation Path Using CNN for Underwater Acoustic Communication. ISCIT 2021: 59-60 - [c45]Takahiro Ishikawa, Shingo Yoshizawa:
RAKE Reception of OFDM Signals in Non-Line-of-Sight Underwater Acoustic Communication. ISPACS 2021: 1-2 - [c44]Atsushi Wada, Shingo Yoshizawa, Satoshi Yuasa, Hideki Sugimoto:
Simultaneous Multi-points Measurement in Underwater Acoustic Localization. ISPACS 2021: 1-2
2010 – 2019
- 2018
- [j24]Shingo Yoshizawa
, Takashi Saito, Yusaku Mabuchi, Tomoya Tsukui, Shin-ichi Sawada:
Parallel Resampling of OFDM Signals for Fluctuating Doppler Shifts in Underwater Acoustic Communication. J. Electr. Comput. Eng. 2018: 3579619:1-3579619:11 (2018) - 2017
- [j23]Tran Thi Thao Nguyen
Low Latency IDMA With Interleaved Domain Architecture for 5G Communications. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 582-593 (2017) - [j22]Shingo Yoshizawa
Data Selective Rake Reception for Underwater Acoustic Communication in Strong Multipath Interference. J. Electr. Comput. Eng. 2017: 5793507:1-5793507:9 (2017) - [c43]Tran Thi Thao Nguyen, Leonardo Lanante
Low latency Interleave Division Multiple Access System. ICOIN 2017: 7-12 - [c42]Tatsuya Abe, Hiroshi Tanimoto, Shingo Yoshizawa:
A simple current reference with low sensitivity to supply voltage and temperature. MIXDES 2017: 67-72 - [c41]Toshiki Sugimoto, Hiroshi Tanimoto, Shingo Yoshizawa:
Comparator design for linearized statistical flash A-to-D converter. MIXDES 2017: 84-89 - [c40]Tran Thi Thao Nguyen
Interleaved Domain Interference Canceller for Low Latency IDMA System and Its VLSI Implementation. VTC Spring 2017: 1-5 - 2016
- [j21]Shingo Yoshizawa, Daichi Sasaki, Hiroshi Tanimoto:
Power Reduction of Variable Wordlength OFDM Receiver in Time-Varying Fading Channels by Monitoring Subcarrier SNRs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(1): 330-337 (2016) - [c39]Shingo Yoshizawa, Hiroshi Tanimoto, Takashi Saito:
SC-FDE vs OFDM: Performance comparison in shallow-sea underwater acoustic communication. ISPACS 2016: 1-5 - 2015
- [j20]Shingo Yoshizawa, Mai Nozaki, Hiroshi Tanimoto:
VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(3): 811-819 (2015) - [c38]Akane Tajima, Shingo Yoshizawa, Hiroshi Tanimoto:
Performance evaluation of antenna diversity with iterative decoding in OFDM-IDMA systems. DSP 2015: 1067-1070 - [c37]Shingo Yoshizawa, Hiroshi Tanimoto:
A low power OFDM receiver monitoring subcarrier SNRs in time-varying fading channels. ISCIT 2015: 229-232 - [c36]Yuji Yokota, Shingo Yoshizawa, Hiroshi Ochi:
ASIP implementation of a low complexity iterative BD precoder for MU-MIMO system. ISCIT 2015: 277-280 - [c35]Toshiki Sugimoto, Hiroshi Tanimoto, Shingo Yoshizawa:
A stochastic flash A-to-D converter with dynamic element matching technique. ISCIT 2015: 307-310 - [c34]Hisato Takehata, Toshiki Sugimoto, Hiroshi Tanimoto, Shingo Yoshizawa:
FPGA implementation of stochastic flash A-to-D converter and its evaluation. ISCIT 2015: 311-314 - [c33]Shun Akada, Shingo Yoshizawa, Hiroshi Tanimoto, Takashi Saito:
Experimental evaluation of data selective rake reception for underwater acoustic communication. ISPACS 2015: 514-519 - 2014
- [j19]Nozomi Miyazaki, Shingo Yoshizawa, Yoshikazu Miyanaga
Low-Power Dynamic MIMO Detection for a 4×4 MIMO-OFDM Receiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(1): 306-312 (2014) - [c32]Mai Nozaki, Shingo Yoshizawa, Hiroshi Tanimoto:
VLSI design of an interference canceller for QPSK OFDM-IDMA systems. APCCAS 2014: 715-718 - [c31]Ryuta Ishimoto, Shingo Yoshizawa, Hiroshi Tanimoto, Takashi Saito:
Evaluation of diversity combining methods for underwater acoustic OFDM communication. ISPACS 2014: 13-16 - 2013
- [j18]Kazi Obaidullah, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
Effects of Channel Features on Parameters of Genetic Algorithm for MIMO Detection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(10): 1984-1992 (2013) - [j17]Yoshikazu Miyanaga
A Robust Speech Communication into Smart Info-Media System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(11): 2074-2080 (2013) - [j16]Kosuke Shimazaki, Shingo Yoshizawa, Yasuyuki Hatakawa, Tomoko Matsumoto, Satoshi Konishi, Yoshikazu Miyanaga
A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(11): 2114-2119 (2013) - [j15]Shingo Yoshizawa
Evaluation of Cover and Reflector in Receiver Antennas for SM-MIMO Wireless Communications. J. Electr. Comput. Eng. 2013: 123827:1-123827:8 (2013) - [j14]Hiroki Iwaizumi
A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems. VLSI Design 2013: 625019:1-625019:10 (2013) - [c30]Kosuke Shimazaki, Shingo Yoshizawa, Yasuyuki Hatakawa, Tomoko Matsumoto, Satoshi Konishi, Yoshikazu Miyanaga
A VLSI design of an arrayed pipelined Tomlinson-Harashima precoder for MU-MIMO systems. APSIPA 2013: 1-4 - [c29]Shingo Yoshizawa, Yasuyuki Hatakawa, Tomoko Matsumoto, Satoshi Konishi, Yoshikazu Miyanaga
Hardware implementation of an interference canceller for IDMA wireless communications. ISPACS 2013: 645-650 - [c28]Shingo Yoshizawa, Masahiro Sugitani, Yoshikazu Miyanaga
Effectiveness of cover and reflector in receiver antennas for MIMO line-of-sight channels. PIMRC 2013: 631-635 - 2012
- [j13]Shingo Yoshizawa, Yoshikazu Miyanaga
Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 550-558 (2012) - [j12]Yusaku Kaneta
A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions. IEICE Trans. Inf. Syst. 95-D(7): 1847-1857 (2012) - [j11]Jaeseong Kim, Shingo Yoshizawa, Yoshikazu Miyanaga
Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN. Integr. 45(2): 132-140 (2012) - [c27]Jaeseong Kim, Shingo Yoshizawa, Yoshikazu Miyanaga
A low-power MMSE MIMO detector using dynamic voltage wordlength scaling for 4×4 MIMO-OFDM systems. ISCAS 2012: 2793-2796 - [c26]Xiaonan Nicole Shi, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
Realistic Rician fading channel based optimal linear MIMO precoding evaluation. ISCCSP 2012: 1-5 - [c25]Hiroki Iwaizumi, Shingo Yoshizawa, Yoshikazu Miyanaga
A new high-speed and low-power LSI design of SVD-MIMO-OFDM systems. ISCIT 2012: 204-209 - 2011
- [j10]Shingo Yoshizawa, Hirokazu Ikeuchi, Yoshikazu Miyanaga
VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4×4 MIMO-OFDM Receiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(1): 324-331 (2011) - [j9]Hisayoshi Kano, Shingo Yoshizawa, Takashi Gunji, Shougo Okamoto, Morio Tawarayama, Yoshikazu Miyanaga
Development and Outdoor Evaluation of an Experimental Platform in an 80-MHz Bandwidth 2×2 MIMO-OFDM System in 5.2-GHz Band. IEICE Trans. Inf. Syst. 94-D(12): 2400-2408 (2011) - [c24]Shingo Yoshizawa, Atsushi Orikasa, Yoshikazu Miyanaga
An area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems. ISCAS 2011: 2705-2708 - [c23]Xiaonan Nicole Shi, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
MIMO precoding performance for correlated and estimated Rician fading. ISCIT 2011: 48-52 - [c22]Kazi Obaidullah, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
Evaluation of genetic algorithm-based detection for correlated MIMO fading channels. ISCIT 2011: 507-511 - [c21]Shingo Yoshizawa, Daisuke Nakagawa, Nozomi Miyazaki, Takaya Kaji, Yoshikazu Miyanaga
LSI development of 8×8 single-user MIMO-OFDM for IEEE 802.11ac WLANs. ISCIT 2011: 585-588 - [c20]Takaya Kaji, Shingo Yoshizawa, Yoshikazu Miyanaga
Development of an ASIP-based singular value decomposition processor in SVD-MIMO systems. ISPACS 2011: 1-5 - [c19]Nozomi Miyazaki, Shingo Yoshizawa, Yoshikazu Miyanaga
Low-power dynamic MIMO detection for a 4×4 MIMO-OFDM receiver. ISPACS 2011: 1-6 - [c18]Kazi Obaidullah, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
Fading effects on parameter selection in genetic algorithm for MIMO detection. ISPACS 2011: 1-6 - [c17]Jun Takizawa, Takaya Kaji, Shingo Yoshizawa, Takashi Gunji, Morio Tawarayama, Yoshikazu Miyanaga
Development of wireless video transmission equipment by cooperating hardware and software in wideband MIMO-OFDM system. ISPACS 2011: 1-4 - 2010
- [c16]Jaeseong Kim, Shingo Yoshizawa, Yoshikazu Miyanaga
Dynamic wordlength calibration to reduce power dissipation in wireless OFDM systems. APCCAS 2010: 628-631 - [c15]Yusaku Kaneta
Dynamic reconfigurable bit-parallel architecture for large-scale regular expression matching. FPT 2010: 21-28 - [c14]Shingo Yoshizawa, Hirokazu Ikeuchi, Yoshikazu Miyanaga
Scalable pipeline architecture of MMSE MIMO detector for 4×4 MIMO-OFDM receiver. ISCAS 2010: 2534-2537 - [c13]Shingo Yoshizawa, Shinya Odagiri, Yasuhiro Asai, Takashi Gunji, Takashi Saito, Yoshikazu Miyanaga
Development and outdoor evaluation of an experimental platform in an 80-MHz bandwidth 2×2 MIMO-OFDM system at 5.2-GHz band. PIMRC 2010: 1049-1054
2000 – 2009
- 2009
- [j8]Chusit Pradabpet, Shingo Yoshizawa, Yoshikazu Miyanaga
New PAPR Reduction in an OFDM System Using Hybrid of PTS-CAPPR Methods with GA Coded Side Information Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(11): 2830-2836 (2009) - [c12]Shingo Yoshizawa, Yoshikazu Miyanaga
VLSI Implementation of a 4×4 MIMO-OFDM transceiver with an 80-MHz Channel Bandwidth. ISCAS 2009: 1743-1746 - 2008
- [j7]Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga:
VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 x 4 MIMO-OFDM Receiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(7): 1757-1762 (2008) - [j6]Chusit Pradabpet, Shingo Yoshizawa, Yoshikazu Miyanaga
New PAPR Reduction in OFDM System Using Hybrid of PTS-APPR Methods with Coded Side Information Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(10): 2973-2979 (2008) - [j5]Shingo Yoshizawa, Yoshikazu Miyanaga
Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(9): 2848-2859 (2008) - [c11]Shingo Yoshizawa, Kazuto Nishi, Yoshikazu Miyanaga
Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems. ISCAS 2008: 1248-1251 - [c10]Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga
A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver. ISCAS 2008: 2486-2489 - 2007
- [c9]Takayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga
Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems. ISCAS 2007: 2287-2290 - [c8]Shingo Yoshizawa, Yoshikazu Miyanaga
Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. ISCAS 2007: 3175-3178 - 2006
- [j4]Shingo Yoshizawa, Yoshikazu Miyanaga
Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(10): 2866-2873 (2006) - [j3]Shingo Yoshizawa, Naoya Wada, Noboru Hayasaka, Yoshikazu Miyanaga
Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(1): 70-77 (2006) - [c7]Shingo Yoshizawa, Yoshikazu Miyanaga
VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System. APCCAS 2006: 93-96 - [c6]Naoya Wada, Noboru Hayasaka, Shingo Yoshizawa, Yoshikazu Miyanaga:
Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction. ISCAS 2006 - [c5]Shingo Yoshizawa, Yoshikazu Miyanaga:
Tunable word length architecture for low power wireless OFDM demodulator. ISCAS 2006 - [c4]Shingo Yoshizawa, Yoshikazu Miyanaga, Hiroshi Ochi, Yoshio Itoh, Nobuo Hataoka, Baiko Sai, Norihisa Takayama, Masaki Hirata:
300-Mbps OFDM baseband transceiver for wireless LAN systems. ISCAS 2006 - 2005
- [j2]Shingo Yoshizawa, Noboru Hayasaka, Naoya Wada, Yoshikazu Miyanaga:
VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform. J. Robotics Mechatronics 17(4): 447-455 (2005) - [c3]Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga
Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. ISCAS (1) 2005: 25-28 - 2004
- [j1]Shingo Yoshizawa, Noboru Hayasaka, Naoya Wada, Yoshikazu Miyanaga:
Cepstral Amplitude Range Normalization for Noise Robust Speech Recognition. IEICE Trans. Inf. Syst. 87-D(8): 2130-2137 (2004) - [c2]Shingo Yoshizawa, Noboru Hayasaka, Naoya Wada, Yoshikazu Miyanaga:
Cepstral gain normalization for noise robust speech recognition. ICASSP (1) 2004: 209-212 - [c1]Shingo Yoshizawa, Naoya Wada, Noboru Hayasaka, Yoshikazu Miyanaga:
Scalable architecture for word HMM-based speech recognition. ISCAS (3) 2004: 417-420
Coauthor Index
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