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Chien-Chang Peng
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2010 – 2019
- 2015
- [j7]Xin-Xiang Lian, I-Chyn Wey, Chien-Chang Peng, Zhi-Qun Cheng:
Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications. IEICE Electron. Express 12(3): 20141122 (2015) - [j6]I-Chyn Wey, Bing-Chen Wu
, Chien-Chang Peng, Cihun-Siyong Alex Gong, Changhong Yu:
Robust C-element design for soft-error mitigation. IEICE Electron. Express 12(10): 20150268 (2015) - [j5]I-Chyn Wey, Chien-Chang Peng, Feng-Yu Liao:
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 78-87 (2015) - 2014
- [j4]I-Chyn Wey, Chien-Chang Peng, Heng-Jui Chou, Po Tsang Chen:
Reliable and low error dual modular redundancy FIR filter with wide protection window. IEICE Electron. Express 11(9): 20140183 (2014) - [j3]I-Chyn Wey, Chien-Chang Peng, Hwang-Cherng Chow:
Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits. Int. J. Circuit Theory Appl. 42(5): 529-541 (2014) - [j2]I-Chyn Wey, Yu-Sheng Yang, Bing-Chen Wu
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design. Microelectron. J. 45(1): 1-13 (2014) - 2013
- [j1]I-Chyn Wey, Yi-Jung Lan, Chien-Chang Peng:
Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design. Microelectron. Reliab. 53(12): 2057-2069 (2013)
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